PUBLICATIONS
Papers
[C] Seul Ki Han, "A Reference Voltage Generator Using Level Tracking Scheme for Low-Swing PAM-3 Decoding", International SoC Design Conference, 2024 (Accepted)
[C] Hyun-Bin Lee, "A 1.62 – 8.1 Gb/s Reference-less Digital Clock and Data Recovery for Harmonic-Lock-Free Frequency Acquisition", IEEE ISCAS, 2024
[C] Minji Kim, "Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation", ICEIC, 2024
[C] Hyun-Bin Lee, "An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate Clock and Data Recovery ", International SoC Design Conference, 2023
[J] Eun-Young Jung, "A Duty Cycle Corrector with Dual Loop Low Pass Filter for Low Jitter and Fast Correction Time", International Journal of Electronics and Communications, Apr. 2023
[C] Yoon Heo et al., "Dual Mode All Digital Clock and Data Recovery Circuit for Ultra-low Power Intelligent Edge SoC", ICEIC, 2023
[J] Sang-Hun Lee, Won-Young Lee, "A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction", Sensors, Aug. 2022
[C] Yoon Heo, Won-Young Lee, "A Wide Range Digitally Controlled Oscillators with Direct Proportional Loop Control", International SoC Design Conference, 2022
[J] Dong-Wan Ko, Won-Young Lee, "A Single-Ended Transmitter with Low Switching Noise Injection and Quadrature Clock Correction Schemes for DRAM Interface", IEEE ACCESS, May 2022
[C] Giryong Lee, Won-Young Lee, "A 1.0-V 12-Gb/s Two-FIR Tap DFE with Tap Weighting Adjustable Filters", ICEIC 2022
[J] Chae Young Jung, Won-Young Lee, "A digital clock and data strobe aligner for write calibration of DRAM," IET Electronics Letters, Jan. 2022
[C] Sang-Hun Lee, Won-Young Lee, "A 0.6-V 400-KS/s Low Noise Asynchronous SAR ADC With Dual-domain Comparison", International SoC Design Conference, 2021
[J] Sang-Hun Lee, Won-Young Lee, "Design of ZQ Calibration Circuit using Time domain Comparator", Korea Institute of Electronics Communication Science, 2021
[C] Dong-Wan Ko, Won-Young Lee, "A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector", IEEE International Symposium on Circuits and Systems, 2021
[C] Eun-Young Jung, Won-Young Lee, "A Fast Locking Duty Cycle Corrector with High Accuracy," International SoC Design Conference, 2020
[J] Moon-Chang Shin, Won-Young Lee, "A Driver's Condition Warning System using Eye Aspect Ratio," Korea Institute of Electronics Communication Science, 2020
[J] Chae Young Jung, Won-Young Lee, "A Low Jitter Delay-Locked Loop for Local Clock Skew Compensation," Korea Institute of Electronics Communication Science, 2019
[J] Hyun-Chan Moon, Hong-Ju Kal, Won-Young Lee, "Study on Structure and Principle of Linear Block Error Correction Code," Korea Institute of Electronics Communication Science, 2018
[J] Hong-Ju Kal, Hyun-Chan Moon, Won-Young Lee, "Design of BCH Code Decoder using Parallel CRC Generation," Korea Institute of Electronics Communication Science, 2018
[J] Won-Young Lee, Chae Young Jung, "On-chip Data Strobe Transmission with Short-Circuit Current Protection Scheme for DRAM," IET Electronics Letters, 2018
[J] Won-Young Lee, Chae Young Jung, Ara Cho, "A Clock and Data Recovery Circuit with Adaptive Loop Bandwidth Calibration and Idle Power Saved Frequency Acquisition," IEIE Journal of Semiconductor Technology and Science, 2017
[J] Taehoon Kim, Hyukjae Jang, Won-Young Lee, "An Inter-floor Noise Prevention System using an Open-source Controller," Korea Institute of Electronics Communication Science, 2017
[J] Jae-Sung Yoon, Jeonghyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim, "A Unified Graphics and Vision Processor with a 0.89µW/fps Pose Estimation Engine for Augmented Reality," IEEE Transactions on Very Large Scale Integration Systems, 2013
[J] Won-Young Lee, Jiehwan Oh, Lee-Sup Kim, "A LOG-induced SSN Tolerant Transceiver for On-chip Interconnects in COG-packaged Source Driver IC for TFT-LCD," IEEE Transactions on Circuits and Systems-II, 2013
[J] Won-Young Lee, Kyu-Dong Hwang, Lee-Sup Kim, "A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort version 1.2 with Multi-rate Operation Scheme," IEEE Transactions on Circuits and Systems-I:Regular Papers, 2012
[J] Won-Young Lee, Lee-Sup Kim, "A 5.4 Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme with Minimal Phase Noise Degradation," IEEE Transactions on Circuits and Systems-I:Regular Papers, 2012
[J] Won-Young Lee, Lee-Sup Kim, "An Adaptive Equalizer with the Capacitance Multiplication for DisplayPort Main Link in 0.18 μm CMOS Logic Process," IEEE Transactions on Very Large Scale Integration Systems, 2012
[J] Won-Young Lee, Lee-Sup Kim, "A Spread Spectrum Clock Generator for DisplayPort Main Link," IEEE Transactions on Circuits and Systems-II, 2011
[C] C.-K. Lee, M. Ahn, D. Moon, K. Kim, Y.-J. Eom, W.-Y. Lee, J. Kim, S. Yoon, B. Choi, S. Kwon, J.-Y. Park, S.-J. Bae, Y.-C. Bae, J.-H. Choi, S.-J. Jang and G. Jin, "A 6.4Gb/s/pin at Sub-1V Supply Voltage TX-Interleaving Technique for Mobile DRAM Interface," IEEE Symposia on VLSI Technology and Circuits, 2015
[C] Won-Young Lee and Lee-Sup Kim, "A 5.4 Gb/S Clock and Data Recovery Circuit Using the Seamless Loop Transition Scheme Without Phase Noise Degradation," IEEE International Symposium on Circuits and Systems, 2011
[C] Sang-Hye Chung, Kyu-Dong Hwang, Won-Young Lee, and Lee-Sup Kim, "A High Resolution Metastability-Independent Two-Step Gated Ring Oscillator TDC with Enhanced Noise Shaping," IEEE International Symposium on Circuits and Systems, 2010
[C] Jae-Sung Yoon, Jeonghyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, and Lee-Sup Kim, "A Graphics and Vision Unified Processor with a 0.89uW/fps Pose Estimation Engine for Augmented Reality," IEEE International Solid-State Circuit Conference , 2010
[C] Won-Young Lee, Lee-Sup Kim, "A Spread Spectrum Clock Generator with Spread Ratio Error Reduction Scheme for DisplayPort Main Link," IEEE International Symposium on Circuits and Systems , 2009