PEOPLE

Professor :  Won-Young Lee 

Members 

• • Lee, Youngmin (Master Candidate)

       - Research Interest : Multi-level Equalization & Receiver

• • Lee, Hyun-Bin (Master Candidate)

       - Research Interest : Digital Clock and Data Recovery

• • Jo, Hangmin (Master Candidate)

       - Research Interest : Multi-level Signal-ended Interface

• • Kim, Minji (Master Candidate)

       - Research Interest : Digital Clock and Data Recovery

• • Han, Seulgi (Master Candidate)

       - Research Interest : High-speed Interface with Encoded Signaling

• • Kang, Sunyoung (Undergraduate Researcher - BS&MS program)

       - Research Interest : DRAM Interface

• • Kim, Seunggyun (Undergraduate Researcher - BS&MS program)

       - Research Interest : Clock and Data Recovery for Multi-level Signaling

• • Ryu, Hee-Chul (Master Candidate)

       - Research Interest : High-speed Interface

Alumni

• • Heo, Yoon (M.S., LX Semicon)

  • Lee, Giryong (M.S., Hanhwa System)

  • Lee, Sang-Hun (M.S., Samsung Electronics)

  • Park, Sang-Beom (B.S., Samsung Electronics)

  • Ko, Dongwan (M.S., Samsung Electronics)

  • Jung, Eun-Young (M.S., Samsung Electronics)

  • Jung, Chae-Young (B.S., SK Hynix)

  • Cho, Ara (B.S., Samsung Electronics)