Publications

(108 elements, as of Nov. 12, 2023)

Books (1)

1. L. Amarú, "New Data Structures and Algorithms for Logic Synthesis and Verification", Springer International Publishing, 2016.

Book chapters (2)

1. L. Amarú, P.-E. Gaillardon, S. Mitra, De Micheli, "Exploratory Logic Synthesis for Multiple Independent Gate FETs," Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), IET, 2019, In press.

2. P.-E. Gaillardon, J. Zhang, L. Amarú, G. De Micheli, "Multiple-Independent-Gate Nanowire Transistors: From Technology to Advanced SoC Design," Nano-CMOS and Post-CMOS Electronics: Devices and Modeling (Eds.: S. P. Mohanty, A. Srivastava), IET, 2015, In press.

Journals (13)

1. E. Mlinar, S. Whiteley, A. Belov, S. Chen, L. Amarù, T. Liu, Y. Zhang, T. Arifin, M. Pan, T. Barbee, R. Singh, A. Ajami, D. Rawlings, G. Meuli, R. Kumar, A. Salz, S. Chase, J. Kawa, "An RTL-to-GDSII Flow for Single Flux Quantum Circuits Based on an Industrial EDA Toolchain", IEEE Transactions on Applied Superconductivity, 2023.

2. E. Testa, L. Amarù, M. Soeken, A. Mishchenko, P. Vuillod, P.-E. Gaillardon, G. De Micheli, "Extending Boolean Methods for Scalable Logic Synthesis", IEEE Access 2020.

3. E. Testa, M. Soeken, L. Amarù, W. Haaswijk, G. De Micheli, "Mapping Monotone Boolean Functions into Majority", IEEE Transactions on Computers  (TC), 2018.

4. E. Testa, M. Soeken, L. Amarù, G. De Micheli, "Logic Synthesis for Established and Emerging Computing", Proceedings of the IEEE, 2018.

5. M. Soeken, L. Amarù, P.-E. Gaillardon, G. De Micheli, "Exact Synthesis of Majority-Inverter Graphs and Its Applications", accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.

6. L. Amarù, P.-E. Gaillardon, A. Chattopadhyay, G. De Micheli, "A Sound and Complete Axiomatization of Majority-n Logic", IEEE Transactions on Computers  (TC), 2016.

7. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Majority-Inverter Graph: A New Paradigm for Logic Optimization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.

8. L. Amarù, P.-E. Gaillardon, S. Mitra, G. De Micheli, "New Logic Synthesis as Nanotechnology Enabler", Proceedings of the IEEE, 2015.

9. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Biconditional Binary Decision Diagrams: A Novel Canonical Representation Form", IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2014.

10. L. Amarù, P.-E. Gaillardon, G. De Micheli, "A Circuit Synthesis Flow for Controllable-Polarity Transistors", IEEE Transactions on Nanotechnology, 2014.

11. L. Amarù, P.-E. Gaillardon, J. Zhang, G. De Micheli, "Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors", IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 60, num. 10, p. 672-676, 2013.

12. P.-E. Gaillardon, L. Amarù, S. K. Bobba, M. De Marchi, D. Sacchetto et al. "Nanosystems: Technology and Design" (invited paper), Philosophical Transactions of the Royal Society of London A, vol. 372, num. 2012, 2014.

13. L. Amaru, M. Martina, G. Masera, "High Speed Architectures for Finding the First two Maximum/Minimum Values", IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Vol. 20, Issue 12, pp. 2342-2346, Dec. 2012.

Conferences (68)

1. D. Marakkalage, E. Testa, W. Lau Neto, A. Mishchenko, G. De Micheli, L. Amarù, "Scalable Sequential Optimization Under Observability Don't Cares," Design, Automation and Test in Europe (DATE), Valencia, Spain, 2024.

2. W. Lau Neto, L. Amarù, V. Possani, P. Vuillod, J. Luo, A. Mishchenko, P.-E. Gaillardon, "Improving LUT-based optimization for ASICs", Design Automation Conference (DAC), San Francisco, USA, 2022.

3. G. Meuli, V. Possani, R. Singh, S.-Y. Lee, A. Tempia Calvino, D. Sudara Marakkalage, P. Vuillod, L. Amarù, S. Chase, J. Kawa, G. De Micheli, "Majority-based design flow for AQFP superconducting family," Design, Automation and Test in Europe (DATE), Antwerp, Belgium, 2022.

4. L. Amarù, V. Possani, E. Testa, F. Marranghello, C. Casares, J. Luo, P. Vuillod, A. Mishchenko, G. De Micheli, "LUT-Based Optimization For ASIC Design Flow", Design Automation Conference (DAC), San Francisco, USA, 2021.

5. W. Lau Neto, M. Trevisan Moreira, Y. Li, L. Amarù, C. Yu, P.-E. Gaillardon, "SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping," Design Automation Conference (DAC), San Francisco, USA, 2021.

6. H.-T. Zhang, J.-H. Jiang, L. Amarù, A. Mishchenko, R. Brayton, "Deep Integration of Circuit Simulator and SAT Solver," Design Automation Conference (DAC), San Francisco, USA, 2021.

7. W. Lau Neto, M. Trevisan Moreira, L. Amarù, C. Yu, P.-E. Gaillardon, "Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization," 26th Asia and South Pacific Design Automation Conference ASP-DAC, Tokyo, Japan, 2021.

8. L. Amarù, F. Marranghello, E. Testa, C. Casares, V. Possani, J. Luo, P. Vuillod, A. Mishchenko, G. De Micheli, "SAT-Sweeping Enhanced for Logic Synthesis", Design Automation Conference (DAC), San Francisco, USA, 2020.

9. E. Testa, M. Soeken, H. Riener, L. Amarù, G. De Micheli, "A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks," Design, Automation and Test in Europe (DATE), Grenoble, France, 2020.

10. M. Austin, W. Lau Neto, S. Temple, L. Amarù, X. Tang, P.-E. Gaillardon, "A Scalable Mixed Synthesis Framework for Heterogeneous Networks," Design, Automation and Test in Europe (DATE), Grenoble, France, 2020.

11. W. Lau Neto, M. Austin, S. Temple, L. Amarù, X. Tang, P.-E. Gaillardon, "LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence," Invited paper, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, 2019.

12. W. Lau Neto, X. Tang, M. Austin, L. Amarù, P.-E. Gaillardon, "Improving Logic Optimization in Sequential circuits using Majority-inverter Graphs," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, FL, USA, 2019.

13. E. Testa, M. Soeken, L. Amarù, G. De Micheli, "Reducing the multiplicative complexity in logic networks for cryptography and security applications", Design Automation Conference (DAC), Las Vegas, USA, 2019.

14. H. Riener, E. Testa, W. Haaswijk, A. Mishchenko, L. Amarù, G. De Micheli, M. Soeken, "Scalable generic logic synthesis: one approach to rule them all", Design Automation Conference (DAC), Las Vegas, USA, 2019.

15. E. Testa, L. Amarù, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, C. Casares, P.-E. Gaillardon, G. De Micheli, "Scalable Boolean Methods In A Modern Synthesis Flow", Design, Automation & Test in Europe Conference (DATE), Florence, Italy, 2019.

16. L. Amarù, E. Testa, M. Couceiro, O. Zografos, G. De Micheli, M. Soeken, "Majority logic synthesis", International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, 2018.

17. W. Haaswijk, L. Amarù, P. Vuillod, J. Luo, M. Soeken, G. De Micheli, "Integrated ESOP Refactoring for Industrial Designs", IEEE International Conference on Electronics Circuits and Systems (ICECS), Bordeaux, FRANCE, 2018.

18. H. Riener, E. Testa, L. Amarù, M. Soeken and G. De Micheli, "Size Optimization of MIGs with an Application to QCA and STMG Technologies", IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Athens, Greece, 2018.

19. A. Mishchenko, R. Brayton, A. Petkovska, M. Soeken, L. Amarù, A. Domic, "Canonical Computation without Canonical Representation",  Design Automation Conference (DAC), San Francisco, USA, 2018.

20. L. Amarù, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, J. Olson, R. Brayton, G. De Micheli, "Improvements to Boolean Resynthesis", Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, 2018.

21. D. Bhattacharjee, L. Amarù, A. Chattopadhyay, "Technology-Aware Logic Synthesis for ReRAM based In-Memory Computing", Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, 2018.

22. M. Soeken, W. Haaswijk, E. Testa, A. Mishchenko, L. Amarù, R. Brayton, G. De Micheli, "Practical Exact Synthesis", Invited, Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, 2018.

23. L. Amarù, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, P.-E. Gaillardon, J. Olson, R. Brayton, G. De Micheli, "Enabling Exact Delay Synthesis", International Conference on Computer Aided Design, (ICCAD), Irvine, CA, USA, 2017.

24. Z. Chu, X. Tang, M. Soeken, A. Petkovska, G. Zgheib, L. Amarù, Y. Xia, P. Ienne, G. De Micheli, P.-E. Gaillardon, "Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains", Great Lakes Symposium on VLSI (GLSVLSI), Banff, Alberta, Canada, 2017.

25. L. Amarù, P. Vuillod, J. Luo, J. Olson, "Logic Optimization and Synthesis: Trends and Directions in Industry", Design, Automation & Test in Europe Conference (DATE), Lausanne, Switzerland, 2017.

26. O. Zografos, A. De Meester, E. Testa, M. Soeken, P.-E. Gaillardon, G. De Micheli, L. Amarù, P. Raghavan, F. Catthoor, R. Lauwereins, "Wave Pipelining for Majority-based Beyond-CMOS Technologies", Design, Automation & Test in Europe Conference (DATE), Lausanne, Switzerland, 2017.

27. L. Amarù, M. Soeken, W. Haaswijk, E. Testa, P. Vuillod, J. Luo, P.-E. Gaillardon, G. De Micheli, "Multi-level Logic Benchmarks: An Exactness Study" 22nd Asia and South Pacific Design Automation Conference ASP-DAC, Tokyo, Japan, 2017. 

28. W. Haaswijk, M. Soeken, L. Amarù, P.-E. Gaillardon, G. De Micheli, "A Novel Basis for Logic Rewriting", 22nd Asia and South Pacific Design Automation Conference ASP-DAC, Tokyo, Japan, 2017. 

29. E. Testa, M. Soeken, L. Amarù, P.-E. Gaillardon, G. De Micheli, "Inversion Minimization In Majority-Inverter Graphs" IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Beijing, China, 2016.

30. M. Soeken, S. Shririnzadeh, P.-E. Gaillardon, L. Amarù, R. Drechsler, G. De Micheli, "An MIG-based Compiler for Programmable Logic-in-Memory Architectures," 53rd Design Automation Conference (DAC), 5-9 June 2016, Austin, TX, USA.

31. A. Chattopadhyay, L. Amarù, M. Soeken, P.-E. Gaillardon, G. De Micheli, "Notes on Majority Boolean Algebra," IEEE International Symposium on Multi-Valued Logic (ISMVL), 18-20 May 2016, Sapporo, Japan, Accepted for publication.

32. P.-E. Gaillardon, M. Hasan, A. Saha,  R. Walker,  B. Sensale-Rodriguez, "Digital, Analog and RF Design Opportunities of Three-Independent-Gate Transistors," Invited, IEEE International Symposium on Circuits and Systems (ISCAS) Montreal, Canada, 2016.

33. L. Amarù, P.-E. Gaillardon, R. Wille, G. De Micheli, "Exploiting Inherent Characteristic of Reversible Circuits for Faster Combinational Equivalence Checking," Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, 2016.

34. M. Soeken, L. Amarù, P.-E. Gaillardon, G. De Micheli, "Optimizing Majority-Inverter Graphs with Functional Hashing ," Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, 2016.

35. P.-E. Gaillardon, L. Amarù  A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. De Micheli, "The PLiM Computer: Computing within a Resistive Memory Array," Invited, Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, 2016.

36. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Majority-based Synthesis for Nanotechnologies", invited, Asia and South Pacific Design Automation Conference (ASP-DAC 2016),  Macao, China, 2016.

37. I. P. Radu, O. Zografos, A. Vaysset, F. Ciubotaru, J. Yan, J. Swerts, D. Radisic, B. Briggs, B. Soree, M. Manfrini, M. Ercken, C. Wilson, P. Raghavan, C. Adelmann, A. Thean, L. Amarù,  P.-E. Gaillardon, G. De Micheli, D. E. Nikonov, S. Manipatruni, I. A. Young, "Spintronic majority gates",  IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 205. 

38. W. Haaswijk, L. Amarù, P.-E. Gaillardon, G. De Micheli, "Unlocking NEM Relays Design Opportunities with Biconditional Binary Decision Diagrams", IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Boston, MA, USA, 2015. 

39. O. Zografos, B. Sorée, A. Vaysset, S. Cosemans, L. Amarù, P.-E. Gaillardon, G. De Micheli, C. Adelmann, D. Wouters, R. Lauwereins, S. Sayan, P. Raghavan,  D. Verkest, I. Radu, A. Thean "Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS", IEEE Conference on Nanotechnology (IEEE-NANO), Rome, Italy, 2015. 

40. L. Amarù, P.-E. Gaillardon, A. Mishchenko, M. Ciesielski, G. De Micheli, "Exploiting Circuit Duality to Speed Up SAT", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, FR, 2015. 

41. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Boolean Logic Optimization in Majority-Inverter Graphs", Design Automation Conference (DAC), San Francisco, CA, USA, 2015. 

42. P.-E. Gaillardon, L. Amarù,  A. Siemon, E. Linn, A. Chattopadhyay, G. De Micheli, "Computing Secrets on a Resistive Memory Array", (WIP poster) Design Automation Conference (DAC), San Francisco, CA, USA, 2015. 

43. O. Zografos, B. Sorée, A. Vaysset, S. Cosemans, L. Amarù, P.-E. Gaillardon, G. De Micheli, C. Adelmann, D. Wouters, R. Lauwereins, S. Sayan, P. Raghavan,  D. Verkest, I. Radu, A. Thean "Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS", (WIP poster) Design Automation Conference (DAC), San Francisco, CA, USA, 2015. 

44. S. Miryala, V. Tenace, A. Calimera, E. Macii, M. Poncino, L. Amarù, P.-E. Gaillardon, G. De Micheli, "Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization", Great Lake Symposium on VLSI (GLSVSLI), Pittsburgh, PA, USA, 2015. 

45. A. Chattopadhyay, A. Littarru, L. Amarù, P.-E. Gaillardon, G. De Micheli "Reversible Logic Synthesis via Biconditional Binary Decision Diagrams", IEEE International Symposium on Multiple-Valued Logic (ISMVL 2015),  Waterloo, Canada, 2015.

46. L. Amarù, A. Petkovska, P.-E. Gaillardon, D. Novo, P. Ienne, G. De Micheli, "Majority-Inverter Graph for FPGA Synthesis", Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2015),  Yilan, Taiwan, 2015.

47. J. Broc, L. Amarù, J. J. Murillo, P.-E. Gaillardon, K. Palem, G. De Micheli, "A Fast Pruning Technique for Low-Power Inexact Circuit Design", IEEE Latin American Symposium on Circuits and Systems (LASCAS 2015),  Montevideo, Uruguay, 2015.

48. P.-E. Gaillardon, L. Amarù, G. Kim, X. Tang, G. De Micheli,  "Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion," (Abstract) International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA,  2015.

49. L. Amarù, G. Hills, P.-E. Gaillardon, S. Mitra, G. De Micheli, "Multiple Independent Gate FETs: How Many Gates Do We Need?", Asia and South Pacific Design Automation Conference (ASP-DAC 2015),  Chiba/Tokyo, Japan, 2015.

50. O. Zografos, L. Amaru, P.-E. Gaillardon, G. De Micheli, "Majority Logic Synthesis for Spin Wave Technology", Euromicro Conference on Digital System Design (DSD 2014), Verona, Italy, 2014.

51. O. Zografos, P. Raghavan, L. Amaru, B. Soree, R. Lauwereins, I. Radu, D. Verkest, A. Thean, "System-level Assesment and Area Evaluation of Spin Wave Logic Circuits", IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2014), Paris, France, 2014.

52. P.-E. Gaillardon, L. Amaru, G. De Micheli, "Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis", IEEE Computer Society Annual Symposium on VLSI (ISLVSI), Tampa, Florida, 2014

53. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization," Design Automation Conference (DAC), San Francisco, CA, USA, 2014.

54. L. Amarù, A. Balatsoukas Stimming, P.-E. Gaillardon, A. Burg, G. De Micheli, "Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams", (University Booth) Design, Automation and Test in Europe (DATE), Dresden, Germany, 2014.

55. P.-E. Gaillardon, L. Amaru, J. Zhang, G. De Micheli, "Advanced System on a Chip Design Based on Controllable-Polarity FETs" (invited paper). Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, 2014.

56. L. Amarù, P.-E. Gaillardon, G. De Micheli, "An Efficient Manipulation Package for Biconditional Binary Decision Diagrams", Design, Automation and Test in Europe (DATE), Dresden, Germany, 2014.

57. P.-E. Gaillardon, L. Amarù, G. De Micheli, "A New Basic Logic Structure for Data-Path Computation," (Abstract) International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, USA,  2014.

58. L. Amarù, P.-E. Gaillardon, A. Burg, G. De Micheli, "Data Compression via Logic Synthesis", Asia and South Pacific Design Automation Conference (ASP-DAC 2014), Singapore, 2014.

59. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Efficient Arithmetic Logic Gates Using Double-Gate Silicon Nanowire FETs", (invited paper) IEEE International NEWCAS Conference, Paris, France, 2013.

60. P.-E. Gaillardon, M. De Marchi, L. Amaru, S. Bobba and D. Sacchetto et al. , "Towards Structured ASICs Using Polarity-Tunable SiNW Transistors", (invited paper) 50th Design Automation Conference (DAC 2013), Austin, Texas, USA, 2013.

61. L. Amaru, P.-E. Gaillardon, G. De Micheli, "BDS-MAJ: A BDD-based Logic Synthesis Tool Exploiting Majority Logic Decomposition", Design Automation Conference (DAC 2013), Austin, Texas, USA, 2013.

62. O. Türkyilmaz, L. Amarù, F. Clermidy, P.-E. Gaillardon, G. De Micheli, "Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET", IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013.

63. P.-E. Gaillardon,  L. Amaru, S. Bobba, M. De Marchi, D. Sacchetto et al., "Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs", (invited paper) Design, Automation & Test in Europe Conference (DATE 2013), Grenoble, France, 2013.

64. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions", Design, Automation & Test in Europe Conference (DATE 2013), Grenoble, France, 2013.

65. L. Amarù, P.-E. Gaillardon, G. De Micheli, "MIXSyn: An Efficient Logic Synthesis Methodology for Mixed XOR-AND/OR Dominated Circuits", Asia and South Pacific Design Automation Conference (ASP-DAC 2013), Yokohama, Japan, 2013.

66. A. Mishra, A. Raymond, L. Amaru, G. Sarkis, C. Leroux, P. Meinerzhagen, A. Burg, W. Gross, "A Successive Cancellation Decoder ASIC for a 1024-Bit Polar Code in 180nm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC 2012), Kobe, Japan, 2012. 

67. S. Frache, L. Amaru, M. Graziano, M. Zamboni, "Nanofabric power analysis: Biosequence alignment case study", IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2011), San Diego, California, 2011.

68. M. Vacca, D. Vighetti, M. Mascarino, L. Amaru, M. Graziano, M. Zamboni, "Magnetic QCA Majority Voter Feasibility Analysis", Conference on PhD Research in Microelectronics and Electronics (PRIME 2011), Trento, Italy, 2011 .

Workshops (9)

1. W. Lau Neto, X. Tang, M. Austin, L. Amarù, P.-E. Gaillardon, "Improving Logic Optimization in Sequential circuits using Majority-inverter Graphs", 28th International Workshop on Logic & Synthesis (IWLS), Lausanne, CH, 2019.

2. M. Austin, W. Lau Neto, L. Amarù, X. Tang, P.-E. Gaillardon, "Towards a Novel Logic Synthesis Framework Supervised by Convolutional Neural Network", 28th International Workshop on Logic & Synthesis (IWLS), Lausanne, CH, 2019.

3. H. Riener, E. Testa, W. Haaswijk, A. Mishchenko, L. Amarù, G. De Micheli, M. Soeken, "Logic Optimization of Majority-Inverter Graphs", Workshop MBMV 2019, Kaiserslautern, Germany, 2019.

4. E. Testa, M. Soeken, L. Amarù, P.-E. Gaillardon, G. De Micheli, "Inversion Minimization In Majority-Inverter Graphs" 25th International Workshop on Logic & Synthesis (IWLS), Austin, TX, USA, 2016.

5. W. Haaswijk, M. Soeken, L. Amarù, P.-E. Gaillardon, G. De Micheli, "LUT Mapping and Optimization for Majority-Inverter Graphs," 25th International Workshop on Logic & Synthesis (IWLS), Austin, TX, USA, 2016.

6. L. Amarù, P.-E. Gaillardon, G. De Micheli, "The EPFL Combinational Benchmark Suite," 24th International Workshop on Logic & Synthesis (IWLS), Mountain View, CA, USA, 2015.

7. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Majority Logic Representation and Satisfiability," 23rd International Workshop on Logic & Synthesis (IWLS), San Francisco, CA, USA, 2014.

8. L. Amaru, P.-E. Gaillardon, G. De Micheli, "Biconditional BDD: A Novel BDD Enabling Efficient Direct Mapping of DG Controllable Polarity FETs", Functionality-Enhanced Devices Workshop (FED), Lausanne, Switzerland, 2013.

9. L. Amaru, P.-E. Gaillardon, G. De Micheli, "Logic Synthesis for Emerging Technologies", FETCH conference 2013, Leysin, Switzerland, 2013.

Patents (15)

1. W. Lau Neto, L. Amarù, V. Possani, P. Vuillod, J. Luo, "ASIC Synthesis based on LUT Mapping," PCT, Dec. 2021.

2. L. Amarù, M. Chandraseka, D. Anastasakis, M. Patil, "Boolean Methods For ECO Patch Identification," PCT, Dec. 2021.

3. L. Amarù, V. Possani, E. Testa, F. Marranghello, C. Casares, J. Luo, P. Vuillod, "ASIC Synthesis based on LUT Optimization," PCT, Nov. 2020.

4. L. Amarù, P. Vuillod, J. Luo, "SAT-sweeping Enhanced For Logic Synthesis," PCT, Nov. 2019.

5. L. Amarù, P. Vuillod, J. Luo, W. Haaswijk, "Robust ESOP Refactoring," PCT, Sept. 2018.

6. L. Amarù, E. Testa, P. Vuillod, J. Luo, "Scalable Boolean Optimization," PCT, Sept. 2018.

7. L. Amarù, P. Vuillod, J. Luo, "Improvements to Boolean Resynthesis," PCT, Sept. 2017.

8. L. Amarù, P. Vuillod, J. Luo, "Exact Delay Synthesis," PCT 15/382,406, Dec. 2016.

9. P.-E. Gaillardon, L. Amarù, R. Vazrala, "An Innovative CPU+FPGA Framework for SAT Solvers Driven by a Highly Parallelized Algorithm," Application, US 62/411,048, 21 October 2016.

10. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Boolean Logic Optimization in Majority-Inverter Graphs," US 14/668,313, 1 June 2015.

11. L. Amarù, P.-E. Gaillardon, G. De Micheli, "A Method and a System for Checking Tautology or Contradiction in a Logic Circuit," US 62/049,435, 12 September 2014.

12. P.-E. Gaillardon, L. Amarù, G. Kim, X. Tang, G. De Micheli,  "Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion," PCT IB2014/064659, 19 September 2014.

13. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Majority Logic Synthesis," PCT IB2014/059133, 20 February 2014.

14. P.-E. Gaillardon, L. Amarù, G. De Micheli, "A New Basic Logic Structure for Data-path Computation," PCT IB2014/059123, 20 February 2014.

15. L. Amarù, P.-E. Gaillardon, G. De Micheli, "Controllable Polarity FET based Arithmetic and Differential Logic," EP 12179928.2, 9 August 2012, US 13/960,964 11, 7 August 2013, US 2014-0043060 A1, 13 February 2014.

Invited Talks

• L. Amarù, "Advances in Industrial Logic Synthesis", Invited, University of Utah, USA, 2021.

• L. Amarù, "Advances in Industrial Logic Synthesis", Invited, University of Southampton, UK, 2020.

• L. Amarù, "Practical Majority Logic Synthesis", Tutorial, International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, 2018.

• L. Amarù, "Logic Optimization for Delay, Area and Power in ICs", Invited, IEEE CASS Seasonal School on Logic Synthesis, August 2018, Porto Alegre, Brazil.

• L. Amarù, "Advances in Industrial Logic Synthesis", Invited, EPFL Workshop on Logic Synthesis and Emerging Technologies, September 2017, Lausanne, Switzerland.

• L. Amarù, "Delay-Oriented Logic Synthesis", Tutorial, Design Automation Conference (DAC), 2017,  Austin, Texas, USA.

• L. Amarù, "Advances in Industrial Logic Synthesis",  UC Berkeley (Prof. R. Brayton),  Nov. 2016, Berkeley, California, USA.

• L. Amarù, "The Majority Logic Optimization Paradigm", EPFL Workshop on Logic Synthesis & Verification, December 2015, Lausanne, Switzerland.

• L. Amarù, "Synthesis and Verification of Arithmetic Circuits", Tutorial, International Conference on Computer Design (ICCD'15), October 2015, New York City, New York, USA.

• L. Amarù, "Exploiting New Logic Primitives: Opportunities for Synthesis and Verification", Italian Annual Seminar Day on Logic Synthesis, June 2015, Rome, Italy.

• L. Amarù, "Exploiting New Logic Primitives: Opportunities for Synthesis and Verification", UC Berkeley (Prof. R. Brayton),  June 2015, Berkeley, California, USA.

• L. Amarù, "Exploiting New Logic Primitives: Opportunities for Synthesis and Verification", Synopsys Inc., June 2015, Mountain View, California, USA.

• L. Amarù, "Electronic Design Automation for Nanotechnologies", Tutorial, Asia and South Pacific Design Automation Conference (ASPDAC'15), January 2015, Tokyo, Japan.

• L. Amarù, "Majority and Biconditional Logic: Extending the Capabilities of Modern Logic Synthesis", International Workshop on Emerging Technologies of Synthesis and Optimization, December 2014, Shanghai, China.  

• L. Amarù, "Majority and Biconditional Logic: Extending the Capabilities of Modern Logic Synthesis", Italian Annual Seminar Day on Logic Synthesis, August 2014, Verona, Italy.

• L. Amarù, "Majority and Biconditional Logic: Extending the Capabilities of Modern Logic Synthesis", UMIC Center (Prof. A. Chattopadhyay), July 2014, RWTH, Aachen, Germany.

• L. Amarù, "Majority and Biconditional Logic: Extending the Capabilities of Modern Logic Synthesis", UC Berkeley (Prof. R. Brayton),  May 2014, Berkeley, California, USA.

• L. Amarù, "Majority and Biconditional Logic: Extending the Capabilities of Modern Logic Synthesis", Synopsys Inc., May 2014, Mountain View, California, USA.