Short bio

Luca Amaru is Executive Director, R&D in the EDA Group of Synopsys Inc., Sunnyvale, CA, USA. He is responsible for designing the next generation of logic synthesis technologies. When not coding, Dr. Amaru leads an exceptional team of R&D engineers focusing on logic synthesis.

Previously, he was research assistant at EPFL, Integrated Systems Laboratory, Lausanne, Switzerland (2011-2015), and visiting researcher at Stanford University, Palo Alto, CA, USA (2014).

Dr. Amaru received his PhD degree in Computer Science from EPFL, Lausanne, Switzerland (2015). He received his double Master's Degree in Electronic Engineering, with honors, from Politecnico di Torino, Turin, Italy, and Politecnico di Milano, Milan, Italy (2011). He received his Bachelor's Degree in Electronic Engineering, with honors, from Politecnico di Torino, Turin, Italy (2009).

At present, Dr. Amaru is author or coauthor of 108 scientific articles and inventor or coinventor of 15 patents.

News

Nov. 29th, 2023: Paper "Scalable Sequential Optimization Under Observability Don't Cares" accepted to DATE'24 has been nominated as Best Paper Award Candidate!
Nov. 12th, 2023: Paper "Scalable Sequential Optimization Under Observability Don't Cares" was accepted by the Design, Automation, and Test in Europe conference!
Nov. 10th, 2023: Dr. Amaru recognized as 2023 AI 2000 Most Influential Scholar Honorable Mention in Chip Technology!
Jun. 14th, 2022: Dr. Amaru receives the 2022 Design Automation Conference (DAC) Under-40 Innovator Award!
May 1st, 2022: Promotion to Principal R&D Engineer!
Apr. 13th, 2022: Dr. Amaru recognized as 2022 AI 2000 Most Influential Scholar Honorable Mention in Chip Technology!
Dec. 12th, 2021: Dr. Amaru is organizing the special session "Novel Design Techniques for Emerging Technologies in Computing" for the Design Automation and Test in Europe Conference 2022!
Oct. 5th, 2021: Dr. Amaru will serve as General Chair for the International Workshop on Logic & Synthesis 2022!
Apr. 2nd, 2021: Dr. Amaru gave a virtual seminar on "Advances in Industrial Logic synthesis" at the University of Utah, ECE Department!
Feb. 25th, 2021: Dr. Amaru has been elevated to the grade of IEEE Senior Member!
Feb. 24th, 2021: 3 papers "LUT-Based Optimization For ASIC Design Flow", "Deep Integration of Circuit Simulator and SAT Solver" and "SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping" were accepted by the Design Automation Conference!
Jun. 27th, 2020: Synopsys acquires rights to use Majority-Inverter Graph (MIG) technology! Synopsys news, EPFL news
May 31st, 2020: Dr. Amaru will serve as Track Chair (2.1 High-Level, Behavioral, and Logic Synthesis and Optimization) for the International Conference On Computer Aided Design, 2020.
Feb. 27th, 2020: Paper "SAT-Sweeping Enhanced for Logic Synthesis" was accepted by the Design Automation Conference!
Jan. 10th, 2020: Dr. Amaru will serve as co-Program Chair for the International Workshop on Logic & Synthesis 2020!
Nov. 7th, 2019: Papers "A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks" and "A Scalable Mixed Synthesis Framework for Heterogeneous Networks" were accepted by the Design, Automation, and Test in Europe conference!
Jun. 1st, 2019: Promotion to Senior R&D Manager!
Mar. 8th, 2019: Dr. Amaru received the Synopsys Design Group Recognition Award (Q1 2019)!
Mar. 1st, 2019: Papers "Scalable generic logic synthesis: one approach to rule them all" and "Reducing the multiplicative complexity in logic networks or cryptography and security applications" were accepted by the Design Automation Conference!
Jan. 15th, 2019: Book Chapter "Exploratory Logic Synthesis for Multiple Independent Gate FETs" is now available at IET Digital Library!
Nov. 9th, 2019: Paper "Mapping Monotone Boolean Functions into Majority" was accepted as short paper by the IEEE Transactions on Computers!
Nov. 2nd, 2018: Paper "Scalable Boolean Methods In A Modern Synthesis Flow" was accepted by the Design, Automation, and Test in Europe conference!
Nov. 2nd, 2018: Dr. Amaru will serve as Program Chair for the International Workshop on Logic & Synthesis 2019!
Oct. 2nd, 2018: The Proceedings of the IEEE paper "Logic Synthesis for Established and Emerging Computing" is now available!
Aug. 22nd, 2018: Dr. Amaru will serve as Program co-Chair for the Reed-Muller Workshop 2019!
Aug. 6th, 2018: Dr. Amaru gave two lectures on "Logic Optimization for Delay, Area and Power in ICs" at the IEEE CASS Seasonal School on Logic Synthesis in Porto Alegre, Brazil!
Jun. 8th, 2018: Paper "Size Optimization of MIGs with Application to QCA and STMG Technologies" was accepted by the International Symposium on Nanoscale Architectures!
Jun. 4th, 2018: Dr. Amaru receives the prestigious IEEE Donald O. Pederson Best Paper Award!
Jun. 4th, 2018: Promotion to Staff R&D Engineer!
Feb. 9th, 2018: Paper "Canonical Computation without Canonical Representation" was accepted by the Design Automation Conference!
Jan. 5th, 2018: Dr. Amaru will serve as Publicity Chair for the International Workshop on Logic & Synthesis 2018!
Nov. 6th, 2017: The executive session "Exact Synthesis and SAT", organized by Dr. Amaru, was accepted by the Design, Automation and Test in Europe conference!

Research Interests

Accelerating logic computing, at both algorithmic and implementation levels, with emphasis on optimization and SAT.
Beyond CMOS design & exploration.
Electronic design automation, with emphasis on logic synthesis and formal verification.
Emerging applications of logic manipulation tools.

Awards and Honors

AI 2000 Most Influential Scholar Honorable Mention in Chip Technology, 2022, 2023.
ACM/IEEE Design Automation Conference (DAC) Under-40 Innovator Award, 2022.
IEEE Senior Member, 2021.
Synopsys DG Recognition Award, 2019.
IEEE Donald O. Pederson Best Paper Award, 2018.
Synopsys Leading Edge Talent Program, 2017.
EDAA Outstanding Dissertation Award, 2016.
EPFL award for outstanding contributions in research, 2015.
Best presentation award at FETCH'13.
Best paper award nomination at ASPDAC'13.
EPFL, I&C School Fellowship, 2011.

Professional Service

Associate Editor, IEEE Transactions on Computer-Aided Design for Integrated Circuits, 2022-2023.
General Chair for the International Workshop on Logic and Synthesis, 2022.
Special Session Chair for the International Workshop on Logic and Synthesis, 2021.
TPC member for the Design Automation Conference (DAC), 2019-2022.
Track Chair (2.1, HLS, LS) for the International Conference On Computer Aided Design (ICCAD), 2020.
Program Chair for the International Workshop on Logic and Synthesis 2019-2020.
Program co-Chair for the Reed-Muller Workshop, 2019.
Publicity Chair for the International Workshop on Logic and Synthesis, 2018.
TPC member for the Design, Automation and Test in Europe (DATE) conference, 2017-2020.
Program Committee for the International Workshop on Logic and Synthesis, 2016-2020.
Session chair at DAC'17, DATE'17, DATE'16, DSD'14, and other conferences
Program Committee for Special Sessions at DSD'14 and DSD'15 conferences.
Reviewer for the journal IEEE Transactions on Computer-Aided Design for Integrated Circuits.
Reviewer for the journal IEEE Transactions on Nanotechnology.
Reviewer for the journal IEEE Transactions on Emerging Topics in Computing.
Reviewer for the journal IEEE Transactions on Very Large Scale Integration Systems.
Reviewer for the journal IEEE Transactions on Circuits and Systems-Part II.
Reviewer for various other journals in circuits, systems, and computers.

Professional Membership

Senior Member of the IEEE.
Member of the ACM.

Elsewhere

E-mail:

luca dot amaru at synopsys dot com
luca dot amaru dot 87 at gmail dot com

Page updated

Google Sites

Report abuse

Luca Amaru's Homepage