Research

Design Methods for Emerging Technologies based Computing Systems

The aim of my research is to provide methods leveraging emerging technologies for the design of computing systems, which is a cross-disciplinary research area bridging device level and system level scientific communities. Figure 1 illustrates a generic design flow for which key features are models, simulations and exploration. Models gather the specificities of technologies and architectures according to a given abstraction level and for perspectives (e.g. energy and cost point of view). Simulations allow fast estimation of performances, power consumption and yield for a given hardware/technology couple. Exploration allows maximizing their adequacy for energy and cost optimization. Both bottom-up and top-down approaches can be automated and implemented into software tools, thus allowing non-specialists to use. While the flow described above is generic, it has been implemented over the past few years for different technologies and in the scope of collaborations:

  • On silicon photonics since 2008. Collaborations with CEA-Leti (FR) [12][11][1], STMicroelectronics (CA) [7][5][6], Ecole Polytechnique de Montreal (CA) [8], UST (HK) [1][3], INRIA (FR) [13][9].

  • On spintronic since 2014. Collaborations with Beihang (CN) and IEF (FR) [10].

  • On double gate FET since 2010. Collaboration with CEA-Leti (FR) [2][4].

Figure 1: design methods are keys to fill the gap between device and system levels

References

[1] Luan H. K. Duong, Zhehui Wang, Mahdi Nikdast, Jiang Xu, Peng Yang, Zhifei Wang, Zhe Wang, Rafael Kioji Vivas Maeda, Haoran Li, Xuan Wang, Sébastien Le Beux, Yvain Thonnart, "Coherent and Incoherent Crosstalk Noise Analyses in Inter/Intra-chip Optical Interconnection Networks", IEEE Transactions on Very Large Scale Integration Systems, 2015.

[2] Nataliya Yakymets, Ian O’Connor, Kotb Jabeur and Sebastien Le Beux. Multi-Level Mapping of Nanocomputer Architectures Based on Hardware Reuse. Accepted for publication in IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), special issue on Computing in Emerging Technologies, 2014.

[3] Luan H.K. Duong, Mahdi Nikdast, Sébastien Le Beux, Jiang Xu, Xiaowen Wu, Zhehui Wang, Peng Yang. A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip. In IEEE Design & Test special issue on Silicon Nanophotonics for Future Multicore Architectures, 2014.

[4] Kotb Jabeur, Ian O'Connor and Sébastien Le Beux. Ambipolar Independent Double Gate FET (Am-IDGFET) for the design of compact logic Structures. In IEEE Transactions on Nanotechnology, DOI 10.1109/TNANO.2014.2306071. 2014.

[5] Sébastien Le Beux, Ian O’Connor, Gabriela Nicolescu, Guy Bois and Pierre Paulin. Reduction Methods for Adapting Optical Network on Chip Topologies to 3D Architectures, Microprocessors and Microsystems, Vol. 37, Issue 1, fb. 2013.

[6] Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Youcef Bouchebaba, Michel Langevin and Pierre Paulin. Combining Mapping and Partitioning Exploration for NoC-Based Embedded Systems. In Journal of Systems Architecture, Special Issue on HW/SW Co-Design: Systems and Networks on Chip , Vol. 56, Issue 7, July 2010, Pages 223-232.

[7] Sébastien Le Beux, Jelena Trajkovic, Ian O’Connor, Gabriela Nicolescu, Guy Bois and Pierre Paulin. Multi-Optical Network on Chip for Large Scale MPSoC. In IEEE Embedded Systems Letters, Vol. 2, Issue 3, Pages 77 - 80, Sept. 2010.

[8] Sébastien Le Beux, Hui Li, Ian O’Connor, Kazem Cheshmi, Xuchen Liu, Jelena Trajkovic and Gabriela Nicolescu. CHAMELEON: CHANNEL Efficient Optical Network-on-Chip.In IEEE International Conference on Design Automation and Test in Europe (DATE), Special Day on Advancing Electronics Beyond CMOS, Dresden, March, 2014.

[9] Martha Johanna Sepulveda Florez, Sébastien Le Beux, Daniel Chillet, Cedric Killian, Jiating Luo, Hui Li, Ian O'Connor, Olivier Sentieys. Communication Aware Design Method for Optical Network-on- Chip. In the proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Turino, 2015.

[10] Qi An, Li Su, Jacques-Olivier Klein, Sébastien Le Beux, Ian O'Connor, Weisheng Zhao. Full-adder circuit design based on all-spin logic device. In IEEE International Symposium on Nanoscale Architectures (NANOARCH) 2015.

[11] Hui Li, Sébastien Le Beux, Yvain Thonnart and Ian O’Connor. Complementary Communication Path for Energy Efficient on-chip Optical interconnects. In proceedings of the 52th IEEE Design Automation Conference (DAC), San Francisco, June, 2015.

[12] Luan H.K. Duong, Mahdi Nikdast, Jiang Xu, Zhehui Wang, Yvain Thonnart, Sébastien Le Beux, Peng Yang, Xiaowen Wu and Zhifei Wang. Coherent Crosstalk Noise Analyses in Ring-based Optical Interconnects. In IEEE International Conference on Design Automation and Test in Europe (DATE), Grenoble, March, 2015..

[13] Jiating Luo, Cédric Killian, Sébastien Le Beux, Daniel Chillet, Hui Li, Ian O'Connor, and Olivier Sentieys. Channel allocation protocol for reconfigurable Optical Network-on-Chip. Workshop on Exploiting Silicon Photonics for energy-efficient high-performance computing (SiPhotonics) at HiPEAC 2015, Amsterdam, Netherlands, January 19-21, 2015