Publications

JOURNAL PAPERS

Wei Liu, Jiao Li and Yong B. Cho," A novel architecture for parallel multi-view HEVC decoder on mobile device " in EURASIP Journal on Image and Video Processing DOI 10.1186/s13640-017-0174-5. March, 2017.
H. D. Tiwari, M. Sharma and Y. B. Cho, "Low cost high throughput pipelined architecture of 2-D 8x8 integer transforms for H.264/AVC", in International Journal of Electronics, Vol. 100, No. 8, pp. 1033-1045, Aug. 2013.
H. D. Tiwari and Y. B. Cho, "Message length adaptive LDPC codes", in Digital signal processing, Vol. 22, No. 6, pp. 1107-1112, Dec. 2012.
H. D. Tiwari, H. N. Bao and Y. B. Cho, "A Parallel IRRWBF LDPC Decoder Based on Stream-Based Processor" in IEEE Transactions on parallel and distributed Systems, Vol. 23, No. 12, pp. 2198-2204, Dec. 2012.
H. D. Tiwari, M. Sharma and Y. B. Cho, "High Throughput Parallel Design of 2-D 8 × 8 Integer Transforms for H.264/AVC", Journal of The Institute of Electronics Engineers of Korea, Vol. 49, No. 8, pp. 27-34, Aug. 2012.
H. D. Tiwari, M. Sharma and Y. B. Cho, "Shared hardware, high throughput implementation of 2D 4 × 4 and 8 × 8 integer transform for H.264/AVC high-profile coders", in AEU- International Journal of Electronics and Communications, Vol 66, No. 7, pp. 521-531, July 2012.
H. D. Tiwari, H. N. Bao and Y. B. Cho, "Flexible LDPC Decoder using Stream Data Processing for 802.11n and 802.16e", in IEEE Transitions on comsumer Electronics, Vol 57, pp. 1505-1512, Nov. 2011.
A. Indriyatmoko, T. Kang, Y. J. Lee, G. I. Jee, Y. B. Cho and J. Kim, "Artificial neural networks for predicting DGPS carrier phase and pseudorange correction" in GPS Solutions, Vol 12, pp.237-247, Sep. 2008.
H.D. Tiwari, Y. Y. Hwang, D. K. Lee, C. M. Kim and Y. B. Cho, "Code length adaptive LDPC architecture" in IEICE Electronics Express, june 2008.
C. M. Kim and Y.B. Cho, “GPS L1-CA/Galileo combine receiver design”, Thesis Paper Institute of control, Robotics and systems, Jan. 2008.
Myung-Suk Byeon, Yil-Mi Shin, and Y.B Cho, "Hardware Architecture for Fast Motion Estimation in H.264/AVC Video Coding", Vol.E89-A No.6 pp.1744-1745, IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer, Jun 2006
Y.B. Cho, “A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices”, Journal of Electronic Testing-Theory and applications, Dec. 2005.
Sung Man Park, C.M. Kim and Y.B. Cho, “Design of The Precise Synchronized Clock Generator using GPS”, Thesis paper of the Institute of Electronics Engineers of Korea. June 2001
Y.B. Cho, “PCI Controller with EMIF/HPI of TMSC6x DSP”, Texas Instruments, DSPS Fest, Video/Imaging Applications, TX, August 3, 2000.
J.H. Lee, K.C. Lee and Y.B. Cho, “Real-Time Multiprocessor Scheduling Algorithm using Neural Network and Its Hardware Design (Korean) ”, Journal of The Institute of Electronics Engineers of Korea, Volt 37CI, No. 4, July 2000.
M.Y. Kim and Y.B. Cho, “Comparisons of Recognition Rates for the Off-line Handwritten Hangul using Learning Codes based on Neural Network (Korean) ”, Journal of IEEE Korea Council, Vol. 2, No. 1 Sep. 1998.
K.H. Choi, K.C. Lee, J.H. Kim, O.J. Jeon and Y.B. Cho, “A Neural Network Algorithm for the Channel Assignment in Cellular Mobile Communications (Korean)”, Journal of The Institute of Electronics Engineers of Korea, Volt 35C, No. 5, May 1998.
K.C. Lee, H.G. Lee and Y.B. Cho, “VLSI Implementation of Switching Optimization Algorithm based on Neural Networks (Korean)”, Journal of CAD and VLSI Design Study Group in The Institute of Electronics Engineers of Korea, Vol. 5, No. 1, Dec. 1996.
Y.H. Jung, J.H. Kim, B.Y. No, H.S. Oh and Y.B. Cho, “Hot Carrier Effects in Sub-micron Scaled Buried-Channel P-MOSFETs (Korean)”, Journal of The Institute of Electronics Engineers of Korea, Vol. 33A, No. 10, Oct. 1996.
S.B. Lee and Y.B. Cho, “A Comparison Between OTA Multiplier and the Modified Gilbert Multiplier for Neural chip of Kohonen’s SOM(Korean)”, Journal of Konkuk University, Vol. 39(2), 1995.
Y.B. Cho, “A Study of Optimization Problems (Korean)”, Journal of Intelligent-Information System, Vol. 2, No. 2, May 1993.
Y.B. Cho, K. Tsuchiya, and Y. Takefuji, "CMOS Analog/Digital Circuits of the Hysteresis McCulloch-Pitts Neuron for Ramsey Number", Analog VLSI Neural Networks, Kluwer Academic Publishers, 1993.
M. Tsuchimura, T. Kurokawa, Y.B. Cho, and Y. Takefuji, "A Parallel Algorithm for the Weapon-Target Assignment Problem", JAPAN Electronic, Information Communication, Vol.J75-D-I, No.7, July 1992.
N. Funabiki, Y. Takefuji, K.C. Lee, and Y.B. Cho, "A Neural Network Parallel Algorithm for the Clique Vertex-Partition Problems", International Journal of Electronics, Vol.72, No.3, July 1992.
Y. Takefuji, K.C. Lee, and Y.B. Cho, "A Comment on O(n2) Algorithms for Graph Planarization", IEEE Trans, on CAD, Vol.10, No.12, December 1991.
T. Kurokawa, K.C. Lee, Y.B. Cho, and Y. Takefuji, "Hysteresis McCulloch-Pitts Neuron", Electronics Letters, Vol.26, No.25, Electronics Letter, December. 1990.

CONFERENCE PAPERS

WEI LIU, SoonYong Kwon, SeoJin Jang,Taehyeoung Son, Yong Beom Cho "Hybrid parallel High Efficiency Video Coding Extensions on Screen Content Coding Decoder on Embedded systems". IEIE 2019
WEI LIU, SangUn Park, WEI LI, MeeZee Lee "Implementation of High Throughput Parallel Architecture for MV-HEVC Encoder". IEIE 2019
Sang Un Park, Tae Pyeong Kim, Zee Mee Lee, Yong Beom Cho. "Method of RTL Debugging When Using HLS for HW Design". ISOCC 2018
WEI LI, WEI LIU, SoonYong Kwon, Yong Beom Cho. "High-throughput HW-SW implementation for MV-HEVC decoder". ISOCC 2018
WEI LIU, SUJING PAN, TaeHoon Yoon, SoonYong Kwon, Yong Beom Cho,"Heterogeneous Distributed HEVC Encoder with SVM ",IPIU 2018
WEI LIU, WEI LI, SUJING PAN, TaeHoon Yoon,,"Learning based MV-HEVC Disparity Compensation", IPIU 2018
WEI LI, WEI LIU, Yong Beom Cho,"Implementation of Real-time Predict for Object Motion Direction Using Mobile Level GPU",IEIE SoC 2017
PAN SUJING, WEI LIU, Yong Beom Cho,"Implementation of HW/SW Co-Design for Selective Motion Estimation",IEIE SoC 2017
Yeong Kwang Park, WEI LIU, Yong Beom Cho,"Implementation of HW/SW Co-design for ECC using SDSoC",IEIE SoC 2017
Wei Liu, Wei Li, Yong B. Cho,"HEVC Encoder for Heterogeneous Embedded platform",IEIE SoC 2017
Wei Liu, Yeong Kwang Park, Yong Beom Cho,"Implementation of HEVC Decoder in Distributed Mobile Embedded System", IEEE CCWC , January 2017
Wei Liu and Yong Beom Cho, "Multiview Video Coding implemented on SoCFPGAs", Altera SoC Developer Conference(ASDF), Sep. 2015.
JongSoo Han, Chan Mo Kim, Yong Beom Cho, "Design Coordinator for power optimizing in USN", 2009년 SOC 학술대회(science conference), May 2009.
Nguyen Xuan Giap, Honey Durga Tiwari, Yong Beom Cho, Chan Mo Kim, "Low Power IMDCT Design on FPGA", 2009년 SOC 학술대회(science conference), May 2009.
Hoang TM Nguyen, Honey Durga Tiwari, Chan Mo Kim, Yong Beom Cho, "Noise Removal with Combination of Erosion and Connected Component Labeling", 2009년 SOC 학술대회(science conference), May 2009.
Trong Phuc Nguyen, Hyo Jin Nam, Honey Durga Tiwari, ChanMo Kim, YongBeom Cho, "Real time Operating System for Multimedia applications in Automobiles", 2009년 SOC 학술대회(science conference), May 2009.
Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim, Yong Beom Cho, "Multiplier design based on ancient Indian Vedic Mathematics", ISOCC, November 2008.
Honey Durga Tiwari, Ganzorig Gankhuyag, Gi Hyun Kim, Chan Mo Kim, Yong Beom Cho, Younggoo Kwon, "Multiplier less fast loss less integer DCT for H.264", ISOCC, November 2008.
Gi Hyun Kim, Honey Durga Tiwari, Chan Mo Kim, Yong Beom Cho, Younggoo Kwon, "Implementation of DCT based OFDM system", ISOCC, November 2008.
C.M. Kim, S.H Im, G.I. Jee and Y.B Cho, “Design of GPS L1-CA/Galileo dual mode receiver”, ICROS January 2008.
Tae Pyeong Kim, HyoJin Nam , Sanglae Kim and Dr. Yong Beom Cho, " Hardware design of interleaved-RS-Golay codes for small wireless system", pg. 585 Vol-2, The 22nd International Technical Conference on Circuits /Systems, Computers and Communications, ITC-CSCC C, July 2007.
Honey Durga Tiwari, Tae Pyeong Kim, Yoonion Hwang, Dae Kyun Lee, and Dr. Yong Beom Cho, "Generic Rate Adaptive Low Density Parity Check Codes", pg. 213 Vol-1, The 22nd International Technical Conference on Circuits /Systems, Computers and Communications, ITC-CSCC C, July 2007.
Yoonion Hwang, Tae Pyeong Kim, Honey Durga Tiwari and Dr. Yong Beom Cho, "Generic Rate Adaptive Low Density Parity Check Codes", pg. 787 Vol-30 No. 2, IEEK Summer Conference July 2007.
Tae Pyeong Kim, Dae Kyun Lee, Honey Durga Tiwari and Dr. Yong Beom Cho, "Generic Rate Adaptive Low Density Parity Check Codes", pg. 781 Vol-30 No. 2, IEEK Summer Conference July 2007.
H.Y Yoonion, H.J Suu, Ganzorig.G and Y.B Cho, "Design of the Integrated multimedia Post-PC using Mobile MPU and FPGA", SOC 학술대회(science conference) 2007, May 2007.
Tae Pyeong Kim, HyoJin Nam and Dr. Yong Beom Cho, "Hardware Design of Interleaved Extended Golay code with Reduced Memory", May 2007 SOC Conference Seoul, South Korea.
Sanglae Kim, Tae Pyeong Kim, HyoJin Nam and Dr. Yong Beom Cho, "Hardware Design of Reed-Solomon code with Golay code", May 2007 Soc Conference Seoul, South Korea.
Dae Kyun Lee, Jung Bonggil, Sanglae Kim and Dr. Yong Beom Cho, "Hardware design of Low Latency LDPC decoder", pg.519 Vol-1, The 14th Korean Conference on Semiconductor Chip design Contest CDC-03, Feb 2007, Seoul, South Korea.
Tae Pyeong Kim, Sanglae Kim and Dr. Yong Beom Cho, “Hardware Design of Decoder of (24, 12, 8) Extended Golay Code and Error Performance Verification using a SoC Platform based on ARM ", The 14th Korean Conference on Semiconductor Feb 2007, Seoul, South Korea.
Bong Su Park and Dr. Yong Beom Cho, “Hardware design of DCT-Based Watermarking system using LDPC codes”, Proceedings of IEEK fall conference 2006.
H. J. Nam, Y. B. Cho, "H.264 Decoder Porting for ARM Core Processor and Get Better Performance by Code Optimize", 2006 SOC Design Technical Society, MAY 2006.
C.M. Kim, J.M Ko, S.H Im, G.I. Jee and Y.B Cho, “A SOPC(System on a Programmable Chip) based 24 ? Channel Galileo/GPS Receiver”, GNSS ASIA 2005, December 2005.
J.M Ko, C.M Kim, S.H Im, G.I. Jee and Y.B Cho, “Implementation of GPS/GALILEO receiver and signal acquisition & tracking using SOPC”, GNSS 2005, December 2005.
1C.M Kim, J.M Ko, S.H Im, G.I. Jee and Y.B Cho, “SoC Design of GPS Receiver”, ITSoC conference 2005, November 2005.
Min Hwan Song and Y.B Cho, "Hardware design of Integer DCT block for H.264/AVC decoder", IT-SoC 2005 & Next Generation PC Fair Nov 2005.
Yil Mi Shin and Y.B Cho, "Hardware design of Inverse CAVLC for H.264/AVC decoder", IT-SoC 2005 & Next Generation PC Fair Nov 2005.
Yil Mi Shin, Myung Suk Byeon and Y.B Cho, "Hardware Architecture for Fast Motion Estimation in H.264/AVC video coding", IT-SoC 2005 & Next Generation PC Fair Nov 2005.
Bong-Kil Jung, Jun Heo and Y.B Cho, "Hardware design of low latency LDPC codes", IT-SoC 2005 & Next Generation PC Fair Nov 2005.
Yong Beom Cho, Hee Jin Yang, Min-Hwan Song and Y.B Cho, "Performance test of DDFS chip using pipelined CORDIC algorithm", The International SoC Design Conference (ISOCC), Oct. 2005.
Bong Gil Jeong, Jin Il and Y.B Cho, "ASIC Design of I2C Master/Slave and its Applications", The International SoC Design Conference (ISOCC), Oct. 2005.
Sang Lae Kim, Bong Gil Jeong, Min Hwan Song and Y.B Cho, "ASIC Design of PCI controller and its Applications", The International SoC Design Conference (ISOCC), Oct. 2005.
Bong Su Park, Seung Ju Yun, Bong Su Chae and Y.B Cho, "ASIC Design of Blind Watermarking Chip Based on the Modified DCT Coefficient", The International SoC Design Conference (ISOCC), Oct. 2005.
C.M. Kim, J.M Ko, S.H Im, G.I. Jee and Y.B Cho, “A Combined Galileo/GPS Receiver Implementation on a SOPC Device”, ION GNSS 2005, September 2005.
Il Mi Shin, Myeong Seok and Y.B Cho, "VLSI Architecture of H.264/AVC CAVLC Decoder Block", International Technical Conference On Circuits/System, Computers and Communications, July 2005.
Jin Il Jeong, Bong Gil Jeong and Y.B Cho, "Design and Implementation of I2C Master Slave", The 12th Korean Conference on Semiconductors Chip Design Contest, Feb. 2005.
Min Hwan Song, Seung Ju Yun, and Y.B Cho "SoC Design for MPEG-4 Decoder with PCI Interface and ALTERA Excalibur TM Platform", The 12th Korean Conference on Semiconductors Chip Design Contest, Feb. 2005.
Jin Il Jung and Y.B Cho, " Hardware design of RTE-LDPC encoder", SOC Design Conference May 2004.
Bong-Kil Jung, Jun Heo and Y.B Cho, "MAX-Log-MAP decoder design for Turbo Codes", SOC Design Conference May 2004
Yil Mi Shin, Ji Hoon Song and Y.B Cho, "Hardware design using Xilinx System Generator", SOC Design Conference May 2004.
Hee Jin Yang, Mi OK Kim, Kang Joo Kim and Y.B Cho, "Hardware design and implementation of digital frequency synthesiser using CORDIC algorithm", SOC Design Conference May 2004.
Hee jin Yang, Min Hwan Song and Y.B Cho, "Hardware software co-design and implementation of MPEG-4 video decoder", SOC Design Conference May 2004.
P.N. Kondekar, Hawn Sool Oh, Young-Bum Cho, Young-Beom Kim, "The effect of static charge imbalance on the on state behaviour of the super junction power MOSFET: Cool MOS", pg. 77 - 80 Vol.1, Fifth International Conference on Power Electronics and Drive Systems, 2003. PEDS 2003.
Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, Andre Ivanov, "Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing," ats, p. 348, 12th Asian Test Symposium (ATS'03), 2003.
C.M. Kim, Y.B. Cho, R.S. Kim, K.K. Kang and G.H. Ha, “Signal Processor for Microwave Vehicle Detector using PLD”, IDEC conference 2003 summer, August 2003.
Jin Il Jung, Jae Hyung Im and Y.B Cho, "Implementation and Design of Serial Pipeline SRFFT", (IDEC) IC DESIGN EDUCATION CENTER Conference in Daejeon Aug 2003.
Hueng Yeol Yoo, Bong Su Chae, Ki Young Kim and Y.B Cho, "Hardware Design and Implementation for SEED Cipher Processor of Dynamic Pipeline Scheduling Architecture", (IDEC) IC DESIGN EDUCATION CENTER in Daejeon Aug 2003.
Bong Su Chae, Sueng Joo Yoon, Jin Il Jung and Y.B Cho, "Hardware design and implementation for DCT based Blind Watermarking system", (IDEC) IC DESIGN EDUCATION CENTER in Gang-won-do Jul 2003.
C.M Kim, K.H Choi and Y.B Cho, “Hardware Design of CMAC Neural Network for Control Applications”, IJCNN 2003, July 2003.
C. M. Kim, Sung Man Park, Min Hwan Song, Woo Jin Lee and Y.B Cho, "DSP Hardware Implementation for Real-time Video/Imaging Applications", Tl Developer Conference Aug 2002.
C. M. Kim, Jin Il Jung, Sung Jin Byeon and Y.B Cho, "Hardware Implementation of Wavelet-based Watermarking System based on the Modified 2-D DWT Algorithm", (IDEC) IC DESIGN EDUCATION CENTER in Daejeon Aug 2002.
Chae Bong Su, Ki Young Kim and Y.B Cho, "CEED encryption processor implementation and design with pipeline structure", (IDEC) IC DESIGN EDUCATION CENTER in Gang-won-do Jun 2002.
Jae Hyung Leem, Jin Il Jung and Y.B Cho, "Hardware design and implementation of serial pipeline split-radix FFT", (IDEC) IC DESIGN EDUCATION CENTER in Gang-won-do Jun 2002.
C.M. Kim, S.H Kang and Y.B. Cho, “Design of Turbo Decoder using SOVA Algorithm”, IDEC conference 2001 summer, August 2001.
C.M Kim and Y.B. Cho, “Design of The Precise Synchronized Clock Generator using GPS”, IEEK-2001. June, June 2001.
C.M Kim, S.H Kang and Y.B Cho, “Hardware Implementation of Turbo Decoder using SOVA Algorithm”, IEEK-CAD & VLSI conference 2001, May 2001.
Bong Su Chae, Young Ho Kim and Y.B Cho, "Implementation and hardware design of Hi-cube parallel computer network router algorithm with neural network", Kyung Hee University May 2001
Sung Jin Byun, Chul Gu Heo and Y.B Cho, "Deign of Switch Box router with neural network", Kyung Hee University May 2001
Jae Hyung Leem, Gang Yuel Lee and Y.B Cho, " Implementation and hardware design of Multi-cast routing algorithm with neural network", Kyung Hee University May 2001
Hyung Lae Cho, Kang Ju Kim and Y.B Cho, "Study of High resolution digital frequency synthesiser for frequency hopping system with CORDIC algorithm", Kyung Hee University May 2001
C.M. Kim and Y.B. Cho, “Design of Correlator for GPS Receiver,” Proc. of IDEC Conference 2001 Spring, Feb. 2001.
Y.N. Park, H.R. Cho and Y.B. Cho, “A Study on Efficient Motion Vector Prediction using New Spatial-Correlation Computation,” Proc. of IDEC Conference 2001 Spring, Feb. 2001.
K.J. Kim and Y.B. Cho, “A Study on High Resolution DDFS using CORDIC,” Proc. Of IDEC Conference 2001 Spring, Feb. 2001.
S.M. Park, C.M Kim and Y.B Cho, “PCI Controller with C6x HPI/DMA Interface for Image Processing Board”, TI DSPS FEST conference 2000, August 2000.
S.M. Park, C.M. Kim and Y.B. Cho, “PCI Controller Design for Frame Grabber,” Proc. Of IDEC Conference 2000 Summer, Aug. 2000. Frame Grabber using FPGA”, IDEC conference 2000, August 2000.
C.M. Kim, H.D. Choi, S.H. Kang and Y.B. Cho, “VLSI Implementation of Turbo Decoder using SOVA Algorithm,” 2000Proc. of IDEC Conference 2000, Feb. 2000.
S.M. Park, C.M. Kim and Y.B. Cho, “PCI Controller with C6x HPI/DMA Interface for Image Processing Board,” Proc. of TI DSPS FEST Conference 2000, Aug.
C.M. Kim and Y.B. Cho, “A Precise Clock Generator using GPS (Korean),” Proc. of 5th IDEC MPW Conference, Oct. 1999.
S.Y. Lee, Y.B. Cho et. al., “Analysis and Design of Active Series Voltage Compensator with Harmonie Current Compensation,” Proc. of EPE '99, Sep. 1999.
D.C. Park, J. Jung, S.Y. Moon, Y.B. Cho, “A HMM Training Algorithm with Query-based Learning for Refinement of Classification Boundary,” Proc. of IJCNN’99, June 1999.
J.H. Kim and Y.B. Cho, “Expanded Neural Network Controller for 3-Level Clos Switch (Korean),” Proc. of 4th IDEC MPW Conference, Jan. 1999.
C.M. Kim and Y.B. Cho, “Accurate Clock Generator using GPS”, IDEC 5th MPW design conference, August 1998.
C.M. Kim and Y.B. Cho, “Design Switch Box Router based on Neural Network (Korean),” Proc. of 3rd IDEC MPW Conference, May 1998.
K.C. Lee, K.H. Choi and Y.B. Cho, “Neural Chip Implementation Channel Assignment (Korean),” Proc. of CAD and VLSI Design Study Group Conference, May 1997.
K.Y. Lee, J.H. Kim and Y.B. Cho, “Neural Chip Implementation for Switch Rearrangement Algorithm (Korean),” Proc. of 97 Information Communication Conference, April 1997.
K.Y. Lee and Y.B. Cho, “VLSI Implementation of Switching Optimization Algorithm based on Neural Networks (Korean),” Proc. of 1st IDEC MPW Conference, Feb. 1997.
K.C. Lee, J.H. Kim and Y.B. Cho, “Channel Assignment Hardware Design in Cellular Mobile Communication using Neural Networks (Korean),” Proc. of AI, Neural Networks, and Fuzzy System Conference, Oct. 1996.
H.G. Lee, M.Y. Kim, and Y.B. Cho, "Switching Optimization Algorithm using Neural Network," Proc. of ICONIP'94 Seoul, October 1994.
Y.B. Cho, T. Kurokawa, Y. Takefuji, and H.S. Kim, "An O(1) Approximate Parallel Algorithm for the n-task-n-person Problem," Proc. of IJCNN'93 Nagoya, October 1993.
Y.B. Cho, N. Funabiki, K.C. Lee and Y. Takefuji, "Analog Maximum Neural Network Circuits using the Switched Capacitor Technique," Proc. of IJCNN'91 Singapore, November 1991.
K.C. Lee, N. Funabiki, Y.B. Cho, and Y. Takefuji, "A Neural Network Computing for the Maximum Clique Problem," Proc. of IJCNN'91 Singapore, November 1991.
N. Funabiki, Y.B. Cho, et. al., "A Neural Network Approach to Broadcasting in Multi-drop Packet Radio Networks," Proc. of IJCNN'91 Singapore, November 1991.

THESISES / DESERTATIONS

Liu Wei, "Implementation of parallel S/W-H/W for 3D-HEVC decoder", Aug. 2016.
Yu Mei Zhen, "High Throughput Multiplierless Design of 32x32 2D-IDCT for High Efficiency Video Coding", Aug. 2014.
Hailan Shi, "Implementation of Hand Gesture Recognition using Depth Information for Mobile environment",Aug. 2013.
John Mduduzi Mudumbe, Multiview Video Coding Optimization using SIMD Operations for Mobile Devices",Aug. 2013.
Baek Gangsu, "Implementation of Real-Time Eye Tracking Interface in Mobile environment, Feb. 2013.
Xiang Jun Zhao, "Unified architecture for error free Integer DCT and Hadamard computation in High Efficiency Video Coding", Feb. 2013.
Lee Jong-hun, "Implementation of ARM Dual-core CPU based Real time H.264 SVC encoder on mobile environment", Aug. 2012.
Honey Durga Tiwari, "Parallel approach to RRWBF Decoding for LDPC Codes", Aug. 2012.
Meeturani Jagdishram Sharma, "Hardware implementation of unified 2D DCT Transform computation for Ultra-HD", Aug. 2012.
Jang Seung ho, "Hardware Implementation of Object Detection and Tracking in HD Video Sequence", Feb. 2012.
Joo Young Song, "Real-time Hand Gesture Recognition in Embedded System",Feb. 2012.
Nguyen Van Thao, "Real-time Implementation of Multi view Video Decoding using Hardware Accelerator", Aug. 2011.
Nguyen Xuan Giap, "Improve H.264 Encoder for High Definition Video", Feb. 2011.
Nguyen Thi Thu Hang, "Real-time H.264/AVC video encoder on mobile environment using ARM-DSP co-processor", Feb. 2011.
Huynh Ngoc Bao," Implementation of Enhanced IRRWBF Decoding Algorithm for LDPC Using SIMD Technology", Feb. 2011.
Harsh Durga Tiwari, "Design of MMSE Equalizer for Two Dimensional DCT based OFDM", Aug. 2010.
Gihyun Kim, "Improvement for Perfomance of OFDM using the Modified 2-D DCT and H/W-S/W verification (Korean)", Aug. 2009.
Ji Feng, "CORDIC Processor design and Its application to SVD hardware design", Feb. 2009.
Sungwoo Jang, "Study of Code Optimization on Based on ARM DSM(Design Simulation Model)IP (Korean)", Feb. 2009.
Ganzorig Gankhuyag, "Implementation of H.264 standard using Inter Wireless MMX technology (Korean)", Feb. 2009.
Daekyun Lee, "Hardware Design and Verification of Rate-Compatible LDPC Encoder and Decoder using Generator Matrix (Korean)", Feb. 2008.
Sangrae Kim, "Implementation of H/W-Accelerator for H.264/AVC Video Encoder (korean)", Feb. 2008.
Taepyeong Kim, "HW/SW Co-Design for Watermakring System in H.264/AVC (Korean)", Feb. 2008.
Yoonion Hwang, "Study on Perfomance of Improvement for LDPC Codes Based on Product Codes and Its verification with H/W design (Korean)", Feb. 2008.
Bongsu Park, "Hardware Design of Digital Watermarking system using LDPC codes (Korean)", Feb. 2007.
Bongkil Jung, "Hardware Design of Low latency LDPC decoder and Error Performance Verification using a SoC Platform based on ARM processor (Korean)", Feb. 2006.
Myungsuk Byeon, "Hardware Architecture for FastMotion Estimation In H.264/AVC Video Coding (Korean)", Feb. 2006.
Chanmo Kim, "Correlator design for GPS L1-CA/GPS L2C/Galileo tripple mode receiver (Korean)", Feb. 2006.
Yilmi Shin, "Design and HW/SW Co-Verification for CAVLC block of the H.264/AVC Video Decoder (Korean)",Feb. 2006.
Miok Kim, Study on Code Optimization of H.264 Video Decoder on High Performance DSP (Korean), Jun. 2006.
Bongsoo Chae, "Blind Watermarking system Based on the Modified DCT Coefficient (Korean)", Feb. 2003.
Hyunglae Cho, "Hardware Design for Reed Solomon Decoder of Modified Recursive Euclid Architecture (Korean)", Feb. 2002.
Kiyoun Kim, "Hardware Design and Implementation for SEED Cipher Process of Dynamic Pipeline Scheduling Architecture (Korean)", Aug. 2001.
K.J. Kim, "Study on High Resolution DDFS for Frequency Hopping System using CORDIC (Korean)", Feb. 2001.
Y.N. Park, "Study on Efficient Motion Vector Prediction Using New Spatial-Correlation Computation Algorithm (Korean)", Feb. 2001.
S.M. Park, "Design of PCI Bus Controller with DSP's HPI and DMA Interface (Korean)", Aug. 2000.
J.Y. Kim, "Study on Hardware Design of Turbo Codes using SOVA Decoding Algorithm (Korean)",Aug. 2000.
J.W. Nam, "Study on Global Routing Algorithm using Neural Network (Korean)", Aug. 2000.
J.H. Lee, "Study on Scheduling Algorithm for Real-Time Multimedia System using Neural Network (Korean)", Feb. 2000.
C.M. Kim, "Study on Load Balancing for Distributed Systems using Neural Network (Korean)", Feb. 1999.
J.H. Kim, "Study on Implementation of Neural Network Controller for Connection Admission Control in ATM Networks (Korean)",Feb. 1999.
K.H. Choi, "Study on Design of Nonlinear System Controllers using CMAC Neural Network (Korean)",Feb. 1999.
K.Y. Lee, "Study on Multicast Routing Algorithm using Neural Network and its Hardware Design (Korean)",Feb. 1998.
K.C. Lee," Study on Real-Time Multiprocessor Scheduling Algorithm using Neural Network and its Hardware Design (Korean)",Feb. 1998.
D.I. Kim," Study on Cell-Blocking Prevention Algorithm using Neural Network and its Hardware Design (Korean)",Feb. 1997.
C.G. Hur, "Study on Design of Switchbox Router using Neural Network (Korean)", Feb. 1997.
J.H. Choi, "Study on Design of Switching Controller with Prevention of Cell-Blocking using Neural Network (Korean)", Aug. 1996.
J.H. Kim, "Study on Gate-Oxide Thickness Dependence of Hot-Carrier Effects in LDD nand p-MOSFET (Korean)",Feb. 1996.
J.H. Kim," Study on Channel Assignment in Cellular Mobile Communications using Neural Network (Korean)",Feb. 1996.
S.B. Lee, "Study on the Design of the General Purpose Hybrid Analog-Digital Neural Chip of Kohonen? SOM (Korean)",Feb. 1995.
M.Y. Kim," Study on the Recognition of the Off-line Handwritten Hangul based on Neural Network using the Feature Extraction Method (Korean)",Feb. 1995.
H.G. Lee," Study on Switching Optimization Algorithm using Neural Network Model and its Hardware Implementation (Korean)",Feb. 1995.

TEXT BOOK

Y.B. Cho, 실무와 예제를 중심으로 한 OrCAD (Guide for exercise and practice using OrCAD (Korean)), Bogdoo Publishers, 2006. 3.
P. Choi, Y.B. Cho, H.S. Mok, D.C. Baik and Y.J. Keum, PSpice 기초와 활용 (Pspice - Basic and Applications (Korean)), Bogdoo Publishers, 1995. 11. (2015. Revised Book)
Y.B. Cho, J.O. Kim, H.H. Kim and S.H. Lee, OrCAD (Korean), Bogdoo Publishers, 1999. 9.
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IP REGISTRATION

USB 2.0 Protocol Layer Core (KIPEX)
The protocol layer of USB 2.0 controller is responsible for all USB data IO and control communications. The protocol layer supports DMA function, USB packet encoding, and USB packet decoding. This protocol layer core is used for implementation of USB 2.0 function controller with Register block, UTMI I/F and Memory controller.
USB2.0 UTMI I/F Core (KIPEX)
The UTMI Interface of USB2.0 controller is establishes communication between function controller and Physical layer.
USB 2.0 Function Controller Core (KIPEX)
USB 2.0 function controller is used for all USB data IO and control communications. The supported features of USB2.0 function controller are AMBA Interface, Support Full/High speed of USB2.0 transfer, Speed Detection of USB transfer mode(Full/High), UTMI I/F standard, DMA function, USB packet encoding, and USB packet decoding.
24 Channel GPS L1-CA Correlator (KIPA)
A GNSS receiver consists of the RF front end, A/D converter, multi-channel correlator and microprocessor. 24 Channel GPS L1-CA Correlator has 24 tracking modules which can acquire and track the GPS L1-CA code according to the control of the microprocessor.
Low-latency LDPC decoder (KIPA)
Low latency LDPC decoder using parallel processing.
AMBA – Asynchronous Memory Interface Core (IPCoS)
The major feature are Support Standard AMBA interface, Configurable read/write latency, Configurable read/write duration, Adaptive to single port or dual port asynchronous memory.
AMBA – Synchronous Memory Interface Core (IPCoS)
The major feature are Support Standard AMBA interface, Configurable read/write latency, Configurable read/write duration, Adaptive to single port or dual port synchronous memory.
AMBA-UART Interface Core (IPCos)
This IP can Support Standard AMBA interface with Configurable Baud Rate and UART Interrupt with Busy flags for TX/RX operation

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