TPU COding Lab

Title: Recursive Self-Improvement on TPUs: Autonomous Optimization for AI and ML Workloads

Venue: AAAI-27 (Tutorial and Labs Forum)

Abstract: As generative artificial intelligence and big data analytics scale to unprecedented computational demands, hardware accelerators, particularly Google’s custom Tensor Processing Units (TPUs), have become indispensable for training and serving massive foundation models and processing data-intensive pipelines. However, extracting peak hardware utilization remains a formidable systems challenge. Standard compiler pipelines and high-level framework abstractions frequently hit memory and fusion boundaries, leaving substantial compute capabilities untapped. Bridging this efficiency gap requires two critical transitions: first, stepping down to low-level custom kernel authoring via Pallas, and second, moving beyond manual, labor-intensive performance tuning by harnessing agentic Recursive Self-Improvement (RSI) loops. This session provides a comprehensive, hands-on journey through the full lifecycle of high-performance TPU acceleration. Attendees will progress systematically from architectural foundations to low-level Pallas kernel authoring (e.g., translating imperative implementations onto TPU hardware), followed by constructing autonomous multi-agent systems that iteratively profile, diagnose, and optimize these kernels. Finally, participants will learn how to rigorously benchmark and quantify the compounding performance gains achieved across successive RSI iterations. 

Materials (Tutorial Slides): TBA

Schedule: TBA

Location: TBA

Sepaker's Biography: Keun Soo YIM holds a Ph.D. in computer science (CS) from the University of Illinois at Urbana-Champaign, an M.Sc. in EECS from Seoul National University, and B.Sc. degrees in CS and EE from Yonsei University, Korea. He has served as an R&D Staff Member at Samsung Advanced Institute of Technology (SAIT) from 2005 to 2008. Since 2012, he has been with Google, Alphabet Inc. in Sunnyvale, California, where he currently serves as a Software Engineering Lead. He has published over 20 journal and conference papers and co-invented over 40 United States patents. Dr. Yim is the recipient of the 17th Samsung Human-tech Thesis Prize (gold for CS&E). He has co-chaired the industry tracks of IEEE ISSRE (2017, 2022) and IEEE PRDC (2022). He actively contributes to the technical program committees for various conferences and workshops, including IEEE ISSRE (2017-2025), IEEE/IFIP DSN (2019-2020, 2025-2026), IEEE IPDPS (2015-2016, 2018), IEEE HiPC (2018), and IEEE/ACM ICSE (NIER 2024). He has also contributed as a reviewer for the IEEE TRANS. COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE TRANS. DEPENDABLE AND SECURE COMPUTING, IEEE TRANS. MOBILE COMPUTING, IEEE TRANS. VLSI, IEEE MICRO, and SOFTWARE TESTING, VERIFICATION, AND RELIABILITY. Dr. Yim is a senior member of IEEE.