Accelerating GenAI/ML Using TPUs (Tutorial)

Title: Accelerating Generative Artificial Intelligence and Machine Learning with Tensor Processing Units

Venue: IEEE International Conference on Big Data 2025 (Tutorial Track)

Abstract: This session serves as a comprehensive codelab and tutorial, providing a guided, hands-on experience for leveraging Google's Tensor Processing Units (TPUs) for machine learning (ML) and generative artificial intelligence (GenAI) workload acceleration. TPUs are custom-designed Application-Specific Integrated Circuits (ASICs) optimized for performing large-scale tensor operations, such as matrix multiplications, which are fundamental to deep learning workloads. This tutorial will cover the setup and initialization of TPU environments in platforms like Google Colab, and demonstrate their use with popular frameworks including TensorFlow, Keras, JAX, and/or PyTorch/XLA. We will explore key concepts focusing on strategies for optimizing model performance as well as debugging and profiling GenAI/ML workloads. The aim is to equip BigData developers with the knowledge to build, train, optimize, and productize deep neural networks and language models efficiently in a production-like setting, highlighting the unique advantages and considerations of working with TPUs for both training and inference tasks.

Materials (Tutorial Slides): TBD

Schedule: TBD

Location: TBD

Sepaker's Biography: Keun Soo YIM holds a Ph.D. in computer science (CS) from the University of Illinois at Urbana-Champaign, an M.Sc. in EECS from Seoul National University, and B.Sc. degrees in CS and EE from Yonsei University, Korea. He has served as an R&D Staff Member at Samsung Advanced Institute of Technology (SAIT) from 2005 to 2008. Since 2012, he has been with Google, Alphabet Inc. in Sunnyvale, California, where he currently serves as a Software Engineering Lead. He has published over 18 journal and conference papers and co-invented over 35 United States patents. Dr. Yim is the recipient of the 17th Samsung Human-tech Thesis Prize (gold for CS&E). He has co-chaired the industry tracks of IEEE ISSRE (2017, 2022) and IEEE PRDC (2022). He actively contributes to the technical program committees for various conferences and workshops, including IEEE ISSRE (2017-2025), IEEE/IFIP DSN (2019-2020, 2025), IEEE IPDPS (2015-2016, 2018), IEEE HiPC (2018), and IEEE/ACM ICSE (NIER 2024). He has also contributed as a reviewer for the IEEE TRANS. COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE TRANS. DEPENDABLE AND SECURE COMPUTING, IEEE TRANS. MOBILE COMPUTING, IEEE TRANS. VLSI, IEEE MICRO, and SOFTWARE TESTING, VERIFICATION, AND RELIABILITY. Dr. Yim is a senior member of IEEE.