Digital Isolation

Fully Integrated On-chip Compact Capacitive Digital Isolation System in CMOS Technology 

The below block diagram shows an application example of on-chip digital isolator based on inductive link barrier between TX-RX blocks, interfaced with gate driver. The input digital signal from the microcontroller is transmitted at Tx followed by an isolation barrier (between the transformer windings) and then detected at Rx. The objective of the isolation barrier is to avoid voltage spikes and ground loops between low-voltage regime (microcontroller) and high-voltage regime (gate driver), by connecting two different ground references to the corresponding Tx and Rx blocks, ensuring reliable and safe communications between different voltage levels of the system. The inductive link is chosen thanks to its high isolation rating and high common mode transient immunity.

The following figure shows the proposed capacitive DI system supporting a single channel one direction data communication, using two dice solution, where the Tx and the isolation capacitor is implemented in one die, while the other die houses the Rx. The isolation capacitor lower plate is constructed on metal 1, and the upper plate is on metal 4, where the latter is serially connected to the Rx die through a short length bond-wire, thus enabling high isolation capability and data communications between both dice. In order to optimize the proposed DI system to support communication protocol in industrial sensor interfaces, the enable signals for the digital links are sent through serial-to-parallel (SPI) interface for channel configuration. 

Related publications on this topic:

I. Altoobaji, A. Hassan, M. Ali, Y. Audet and A. Lakhssassi, "Capacitively Isolated 400 Mbps Data Transfer System with 2 Ns Propagation Delay and 5 kV /µs Common Mode Transient Immunity," 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), Sherbrooke, QC, Canada, 2024, pp. 283-287, doi: 10.1109/NewCAS58973.2024.10666336.

I. Altoobaji, I. Altoobaji, A. Hassan, M. Ali, Y. Audet and A. Lakhssassi, “A Low-Power 0.68-Gbps Data Communication System for Capacitive Digital Isolator With 1.9-ns Propagation Delay,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2023.3344413. 

I. Altoobaji, A. Hassan, M. Ali, M. Nabavi, Y. Audet, and Lakhssassi, “A Fully Integrated 0.6 Gbps Data Communication System for Inductive-Based Digital Isolator with 0.8 ns Propagation Delay and 10−15 BER,” Electronics, vol. 12, no. 15, p. 3336, Aug. 2023, doi: 10.3390/electronics12153336.

I. Altoobaji, M. Ali, A. Hassan, Y. Audet and A. Lakhssassi, "A High Speed Fully Integrated Capacitive Digital Isolation System in 0.35 µm CMOS for Industrial Sensor Interfaces," 2021 19th IEEE International New Circuits and Systems Conference (NEWCAS), Toulon, France, 2021, pp. 1-4, doi: 10.1109/NEWCAS50681.2021.9462788.

I. Altoobaji, M. Ali, A. Hassan, M. Nabavi, Y. Audet and A. Lakhssassi, "A Fully Integrated On-Chip Inductive Digital Isolator: Design Investigation and Simulation," 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, 2020, pp. 868-871, doi: 10.1109/MWSCAS48704.2020.9184560.