Research Works

We report a new approach to realize the Ge CMOS technology based on the recessed channel and source/drain (S/D). The recessed S/D process greatly improves the Ge n-contacts. A record high maximum drain current of 714 mA/mm and trans-conductance of 590 mS/mm, high Ion/Ioff ratio of 1×105 are achieved at channel length of 60 nm on the nFETs. The Imax and gmax start to be comparable to Ge pFETs and are 5 times of the highest value ever reported on Ge nFETs. (Details could be found Here)

We report the first experimental demonstration of Ge CMOS circuits, based on a novel recessed S/D and channel technique. Ultra-scaled non-Si CMOS logic devices with channel lengths from 500 to 20 nm, channel thicknesses of 25 and 15 nm, EOTs of 4.5 and 3 nm and a small width ratio (Wn:Wp=1.2) are realized on a GeOI substrate. The CMOS inverters have high voltage gain of up to 36 V/V, which is the best value among all of the non-Si CMOS by the standard top-down approach. Scalability studies on Ge CMOS inverters down to 20 nm are carried out for the first time. NAND and NOR logic gates are also investigated. (This work is published in IEDM 2014, link)

We report the first experimental demonstration of Ge 3D CMOS circuits, based on the recessed fin structure. Both n-FinFETs and p-FinFETs with channel length from 200 to 20 nm and fin width from 60 to 10 nm are realized on a Ge-on-insulator (GeOI) substrate. The Ge FinFETs show superior gate electrostatic control over planar devices and sub-threshold slope (SS) as low as 93 and 73 mV/dec are obtained on n- and p-FETs, respectively. Combining the n- and p- type 3D devices together, the FinFET CMOS inverters have high voltage gain up to 34 V/V at VDD of 1.4 V, delivering more than 200% improvement over the planar ones at the same Lch of 200 nm.  (This work is published in VLSI 2015, link)

Ge nanowire CMOS circuits are experimentally demonstrated on a Ge on insulator (GeOI) substrate for the first time. The nanowire CMOS devices have channel lengths (Lch) from 100 to 40 nm, nanowire height (HNW) of 10 nm and nanowire widths (WNW) from 40 to 10 nm, and dielectric EOTs of 2 and 5 nm. Four types of Ge MOSFETs: accumulation mode (AM) and inversion mode (IM) nFETs and pFETs are studied in great details. Record low SS of 64 mV/dec and high maximum trans-conductance (gmax) of 1057 µS/µm are obtained on Ge nanowire nFETs. Furthermore, hybrid Ge nanowire CMOS with AM nFET and IM pFET is also first realized. The highest maximum voltage gain reaches 54 V/V.  (This work is published in IEDM 2015)

InAs gate-all-around (GAA) nanowire MOSFETs are experimentally demonstrated for the first time by a top-down approach. Thanks to the well-controlled nanowire release process and the novel ALD high-k/metal gate stack process, InAs nFETs with channel lengthranging from 380 to 20 nm and nanowire width from 60 to 20 nm are achieved. With an EOT of 3.9 nm, high drain current of 4.3 A/mm at Vds = Vgs = 2 V and maximum transconductance of 1.6 S/mm at Vds = 1 V are obtained in a device with WNW = 20 nm and Lch = 180 nm, normalized by the perimeter of the nanowires. (Details could be found Here)

III-V MOSFETs have been intensively studied as a alternative of Si nMOSFET because of their superior electron mobility.  Since

pMOSFETs based on InAs or InGaAs are extremely poor due to their low hole mobility, the co-integration of Ge pMOSFETs and III-V nMOSFETs has been proposed and demonstrated. However, the processes of this hetero-integration are complicated and the performance of the Ge pMOSFETs and III-V nMOSFETs co-integrated are worse than that on the single substrate. Furthermore, in terms of III-V

pMOSFETs, Sb-based materials show promising results , indicating the possible III-V CMOS using As-based materials for nMOSFET and Sb-based materials for pMOSFETs. Meanwhile, InAs and GaSb are well lattice-matched, belonging to the 6.1 .A family. For here, the study on co-integration of InAs/GaSb CMOS has been carried out. InAs nanowires for nMOSFETs and GaSb Fin structures for pMOSFETs on a common substrate have been successfully demonstrated.

 It is found that reducing nanowire dimension leads to higher on-current, trans-conductance and effective mobility due to stronger quantum confinement and the volume inversion effect. Synopsys Sentaurus TCAD  quantum mechanical simulation has been carried out to study the inversion charge distribution inside the nanowires. Volume inversion effect appears at a larger dimension for InGaAs nanowire MOSFET than its Si counterpart. (Details could be found here)

Multiple device structures on various semiconductor materials are studied, including recessed channel Ge MOSFET, InAs GAA MOSFET, GaAs planar MOSFET, InGaAs QW-FET. The simulation well explains the experimental results.

InAs GAA nanowire MOSFET, electron density with different gate bias.

Germanium recessed channel nMOSFET related parameters in device ON and OFF states.