05-HDL AND fpga

OTHER REFERENCES (might be helpful) 

[0] Slide bài giảng (2022, pdf 19 MB) (download)

[1] Douglas L. Perry, VHDL Programming by Example, 4th Edition, 2002

[2] Tống Văn On, Nguyên lý mạch tích hợp: Tập 2 - Lập trình ASIC, NXB Lao động xã hội, 2005

[3] Peter J. Ashenden, The VHDL Cookbook

[4] website của hãng Xilinx: www.xilinx.com

[5] ModelSim Tutorial ver. 6.5b Mentor Graphics (PDF 759 KB) (upload ngày 13.10.2013)

[6] FPGA architectures: Survey and Challenges (download)

[7] VHDL Quick Reference Card 

[8] Pong P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Salability (download)

[9] Pong P. Chu, FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, 2008 (download)

[10] Pong P. Chu, FPGA Prototyping by Verilog Examples: Xilinx Spartan-3 Version, 2008 (download) 

[11] Huỳnh Việt Thắng, Seminar Ứng dụng FPGA trong thực thi các ứng dụng xử lý tín hiệu và học máy, Khoa ĐTVT, 2016 (download)

Since 2019, I deliver this course using the Digilent Basys-3 Development KIT and the Vivado tool chain.

VIVADO 

(Một số thiết kế trên board BASYS3)

• 1. Basys 3 Tutorials: https://www.xilinx.com/support/university/vivado/vivado-teaching-material/hdl-design.html  

  2. Mạch đọc phím bấm chống nẩy - Debounce Logic Circuit (with VHDL example): https://www.digikey.com/eewiki/pages/viewpage.action?pageId=4980758

  3. Giao tiếp với ADC trên Basys3 - Basys 3 XADC Demo: https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-xadc/start 

  4. Nạp chương trình vào bộ nhớ Flash của board BASYS3 - Programming the BASYS3 Board's Non-Volatile Flash Memory through Vivado: https://sites.google.com/a/umn.edu/mxp-fpga/home/vivado-notes/programming-the-basys3-board-through-vivado 

  5. Dual port Data RAM: https://vhdlguru.blogspot.com/2017/11/vhdl-code-for-dual-port-ram-with.html 

Re: In vivado how to generate instantiation template

current_instance instance_name

xilinx::designutils::write_template -template -vhdl

Replace instance_name in first command with the instance name for which you would like to create instantiation template.

Embedded System Design on NEXYS3 FPGA (Spartan-6) (updated 09.10.2018)

• 1. [12] Part 1: Building an Embedded Processor System on Xilinx Nexys3 FPGA: A Tutorial (download)

  2. [13] Part 2: Creating a Custom Peripheral and adding it to a Microblaze Embedded System (download) 

1. Digilent Nexys-3 BSB Support Files for PLB-based Designs (download)

2. Tài liệu tham khảo Đồ án chuyên ngành K11 KTĐT (download)

Labs

1. Nexys 3 Reference manual   

2. Nexys3_Master.ucf 

3. mux2to1_LED (download)

4. Bộ chia tần số từ 100Mhz xuống 1Hz (file VHDL: clock_divider_100MHz_to_1Hz.vhd)

5. Labs will be provided during the course

Number of students enrolled this course

+ Year 2021-2022, Semester 2: Class 18DT (37 students)

+ Year 2020-2021, Semester 2: Class 17DT (121 students)

+ Year 2019-2020, Semester 2: Class 16DT (29 students)

+ Year 2018-2019, Semester 2: Class 15DT (47 students)

+ Year 2018-2019, Semester 1: Class 14DT (18 students)

+ Year 2017-2018, Semester 1: Class 13DT (120 students)

+ Year 2015-2016, Semester 2: Class 12DT (31 students)

+ Year 2015-2016, Semester 1: Class 11DT (27 students)

+ Year 2013-2014, Semester 1: Class 09DT (59 students)

Revision history

• • Page updated by Thang on 16.06.2025

  • Page updated by Thang on 04.01.2021

  • Page updated by Thang on 09.10.2018

  • Page updated by Thang on 12.12.2017

  • Page updated by Thang on 15.08.2016

  • Page updated by Thang on 28.08.2015