Membership of professional bodies and societies

Member IEEE Inc.

Member IEEE Electron device society

Present Research Activity: Compact MOSFET and SOI MOSFET modeling, OPVs and OTFTs, SPICE modeling and parameter extraction using Universal transistor Modeling Software (UTMOST-IV), Verilog-A and mixed mode simulation, Silvaco TCAD for process and device (BJT, MOSFET, CMOS, TFT, OPV, OTFT, OLED, FinFET etc.).

Work Experience:

Senior Appl. Engineer, Silvaco International Singapore (2012 to present)

TCAD for Silicon, III-V, II-VI, IV-IV, or polymer/organic technologies including CMOS, bipolar, high voltage power device, VCSEL, TFT, optoelectronic, LASER, LED, CCD, sensor, fuse, NVM, ferro-electric, SOI, Fin-FET, HEMT, and HBT.

SPICE Modeling

MOS Technology

• • Typically ten to twelve NMOS and PMOS geometries are measured at specified temperature points for DC model

  • Area and sidewall junction capacitances, oxide capacitance and overlap capacitances are measured and parameters extracted

  • Extracted AC models are verified by measuring and simulating ring oscillator data

  • Complete noise characterization for noise voltage and noise current

  • Models available include Level 1,2,3, BSIM1, BSIM3, HV MOS Level 88, BSIM4, PSP, HiSIM HV, HiSIM and EKV

BIPOLAR Technology

• • DC, junction capacitances, AC (s-parameters), temperature measurements for DC

  • Models available include Gummel Poon, Mextram, VBIC

  • Macro models to include parasitic device effects

Other Supported Technologies

• • Diode: Level 1, 2, 3

  • TFT: Poly and Amorphous TFT models

  • SOI: BSIMSOI

Assistant Professor, Department of Physics, Central University of Rajasthan, City Road, Kishangarh, District-Ajmer-305802, Rajasthan, India.

Taught- Mathematical methods in Physics, Classical Electrodynamics and Device physics and continued research work on organic photovoltaics and energy harvesting.

Assistant Professor and Coordinator, Centre for Applied Physics, Central University of Jharkhand, Brambe, Mandar, Lohardaga Road, Ranchi-835 205. (July 2010- July 2011)

Taught- Mechanics, Classical Mechanics, Electromagnetism and Optics, Solid state devices, Basic Electrical and Electronics to integrated M. Sc. and M. Tech students. Carried out extensive research in the area of optoelectronics and work is published in journals like Journal of Applied Physics, JED etc.

Senior Research Fellow (SRF) at Department of Electronics Engineering, IT, BHU, (2007-2010).

Continued working on Modeling and simulation which includes, modeling and simulation of infrared photodetectors based on III-V alloys and II-VI alloys for guided optical fiber communication systems and unguided free space optical communication systems respectively.

Also fabrication and characterization of U.V. and visible photodetectors and photovoltaic devices based on ZnO, Zno-Si heterojunction photodiode, solar cells, LEDs, thin film transistors (TFTs), organic solar cells, OTFTs and organic light emitting diodes (OLEDS) based on organic materials e.g. polyanthranilic acid (PANA), polycarbazole (PCz), PANA CNT and PCz CNT.

Junior Research Fellow (JRF) at Department of Electronics Engineering, IT, BHU, (2005-2007)

Here as a research fellow worked for modeling, simulation, fabrication and Characterization of pn junction diodes, Schottky diodes, MOS capacitors, MOSFETs, thick film resistors and thick film capacitors in Centre for research in microelectronics (CRME) IT-BHU, Varanasi, India

Teaching / Lab Instructorship:

•Taught “Computer Fundamentals and Digital Electronics” B. Sc. Computer Science students in Women’s College, Banaras Hindu University, Varanasi (During 2007-2008).

• Worked as lab Instructor in UG / PG Lab. experiments on Electronic Device Lab and Analog Circuits, Department of Electronics Engineering, IT, BHU, Varanasi (2006-2007).

•Worked as Lab instructor in Optical communication Lab. to conduct of UG / PG Lab. classes, Department of Electronics Engineering, I. T. BHU, Varanasi (2009-2010)

•Working as an Assistant Professor, Department of Physics, Central University of Rajasthan, Kishangarh (Ajmer), India

Lab Development:

•Designed and developed Applied Physics Lab (Mechanics, Electricity and Magnetism, Optics, Electrical Engg. and Electronics Engg. Lab) at Central University of Jharkhand.

•Developing M. Sc. Physics Lab at Central University of Rajasthan.

Areas of Research Interest:

• SPICE modeling and parameter extraction of MOSFET and SOI MOSFET

• TCAD and EDA for process device and parameter extraction

• VLSI and Microelectronics

• Optoelectronic / Photonic Devices - Modeling and Simulation

• Flexible/ Organic / Plastic Electronics (organic photovoltaic (OPV) OTFT, OLED etc)

• Photodetectors for optical communication and sensing applications and optical sources (LEDs and LASERs)

• Fabrication / characterization of inorganic and organic semiconductor optoelectronic devices

• Solar Cells (based on organic and Inorganic materials)

• ZnO thin film based devices

• MEMS/NEMS (Optical and Electrical study)

Knowledge of CAD & Simulation Tools:

MATLAB, MATHEMATICA, Tanner Tools, and Multisim-2001, 2010, Hardware description languages VHDL/Verilog, TCAD

VICTORY Process VICTORY Cell VICTORY Device VICTORY Stress ATHENA ATLAS Interactive Tools Virtual Wafer Fab

TCAD

VICTORY Process is a general purpose 3D process simulator. VICTORY Process includes a complete process flow core simulator and three advanced simulation modules: Monte Carlo Implant, Advanced Diffusion and Oxidation, and Physical Etch and Deposit. Proprietary models, as well as public domain research models, can be easily integrated into VICTORY Process using the open modeling interface.

VICTORY Process is a general purpose 3D process simulator. VICTORY Process includes a complete process flow core simulator and three advanced simulation modules: Monte Carlo Implant, Advanced Diffusion and Oxidation, and Physical Etch and Deposit. Proprietary models, as well as public domain research models, can be easily integrated into VICTORY Process using the open modeling interface.

VICTORY Device is a general purpose 3D device simulator. A tetrahedral meshing engine is used for fast and accurate simulation of complex 3D geometries. VICTORY Device performs DC, AC and transient analysis for silicon-based semiconductor devices, binary, ternary, quaternary and organic material-based devices.

VICTORY Stress is a generic 3D stress simulator designed to calculate stresses and mobility enhancement factors for any 3D structure using comprehensive material stress models, including the dependence of elasticity coefficients on crystal orientation.

ATHENA framework integrates several process simulation modules within a user-friendly environment provided by Silvaco TCAD interactive tools. ATHENA has evolved from a world-renowned Stanford University simulator SUPREM-IV, with many new capabilities developed in collaboration with dozens of academic and industrial partners. ATHENA provides a convenient platform for simulating processes used in semiconductor industry: ion implantation, diffusion, oxidation, physical etching and deposition, lithography, stress formation and silicidation.

Fast and accurate simulation of all critical fabrication steps used in CMOS, bipolar, SiGe/SiGeC, SiC, SOI, III-V, optoelectronic, MEMS, and power device technologies

Accurately predicts multi-layer topology, dopant distributions, and stresses in various device structures

ATLAS enables device technology engineers to simulate the electrical, optical, and thermal behavior of semiconductor devices. ATLAS provides a physics-based, easy to use, modular, and extensible platform to analyze DC, AC, and time domain responses for all semiconductor based technologies in 2 and 3 dimensions.

· Accurately characterize physics-based devices in 2D or 3D for electrical, optical, and thermal performance without costly split-lot experiments

· Solve yield and process variation problems for optimal combination of speed, power, density, breakdown, leakage, luminosity, or reliability

· Fully integrated with ATHENA process simulation software, comprehensive visualization package, extensive database of examples, and simple device entry

· Availability silicon, III-V, II-VI, IV-IV, or polymer/organic technologies including CMOS, bipolar, high voltage power device, VCSEL, TFT, optoelectronic, LASER, LED, CCD, sensor, fuse, NVM, ferro-electric, SOI, Fin-FET, HEMT, and HBT

· Connect TCAD to Tapeout with direct import of ATLAS results into UTMOST for SPICE parameter extraction

VWF is software used for performing Design of Experiments (DOE) and Optimization Experiments. Split-lots can be used in various pre-defined analysis methods. Split parameters can be defined for any of Silvaco’s process, device, parasitic extraction and circuit simulators.

ANALOG / MIXED-SIGNAL / RF

Gateway SmartSpice SmartSpiceRF Harmony UTMOST III UTMOST IV SPAYN

Gateway is schematic Editor

SmartSpice delivers the highest performance and accuracy required to design complex high precision analog circuits, analog mixed-signal circuits, analyze critical nets, characterize cell libraries, etc.. SmartSpice is compatible with popular analog design flows and foundry-supplied device models.

SmartSpiceRF employs a combination of Time-Domain Shooting and Frequency-Domain Harmonic Balance methods to provide accurate simulation of GHz range RF ICs. It accurately and efficiently simulates harmonic distortion, intermodulation products, gains, noise, oscillator’s phase noise in non-linear circuits using SPICE netlists.

UTMOST III generates accurate, high quality SPICE models for analog, mixed-signal and RF applications. UTMOST III is in use worldwide by leading IDMs, foundries and fabless companies to perform data acquisition, device characterization, model parameter extraction and model verification.

· UTMOST III supports the characterization and model extraction for MOS, BJT, Diode, JFET, GaAs, SOI and TFT devices

· UTMOST III provides the widest selection of measurement equipment from a variety of vendors

· Fully interactive, semi-automated or batch-mode operation is supported

· Real-time model tuning using the rubberband feature

· Integrated with Silvaco TCAD Software and SPAYN statistics program for smooth development of pre-silicon models

· Supports all leading SPICE simulators

UTMOST IV represents the next generation in SPICE model optimization software. UTMOST IV provides powerful tool for developing SPICE models. UTMOST IV provides an easy to use tool for the generation of accurate, compact models and macro-models for analog, mixed-signal and RF applications.

Harmony is a single-kernel analog/mixed-signal circuit simulator that dynamically links in the capabilities of the SmartSpice Circuit Simulator and the SILOS Verilog Simulator at run time. Harmony combines accuracy, performance, capacity and flexibility to simulate circuits expressed in Verilog, SPICE, Verilog-A and Verilog-AMS.

SPAYN is a statistical modeling tool for analyzing variances from model parameter extraction sequences, electrical test routines, and circuit test measurements. SPAYN helps to identify the relationship between device or circuit performance variations and the process fluctuations.

CUSTOM IC CAD

Expert Guardian HIPEX ClarityRLC

Expert is a high performance hierarchical IC layout editor with full editing features, large capacity and fast layout viewing. Expert provides high level of design assistance with Netlist Driven Layout and parameterized cells (Pcells).

Guardian provides interactive and batch mode verification of analog, mixed signal and RF IC designs. Integrated with Silvaco's schematic capture and layout editor, Guardian efficiently performs design rule checks (DRC) and layout vs. schematic (LVS) comparisons.

HIPEX is an accurate and fast full-chip hierarchical extraction software that performs extraction of parasitic capacitances and resistances from hierarchical layouts. HIPEX is tightly integrated with the Expert Layout Editor for complete design flow of DRC/LVS and RC parasitic extraction.

ClarityRLC is an efficient and accurate tool that performs reduction of linear parasitic RLC elements in extracted netlists. Tool is based on Scattering-Parameter-Based Macromodeling and Time Domain methods.

INTERCONNECT

EXACT QUEST CLEVER STELLAR

EXACT delivers the most accurate interconnect models for nanometer semiconductor processes and generates full chip layout parameter extraction (LPE) rule files. EXACT’s powerful 3D field solver and scripting language allows support for any full chip parasitic extractor.

QUEST calculates 3D frequency dependent inductance, resistance, capacitance and capacitive loss for any multi-port network for RF SPICE analysis. QUEST creates frequency dependent and independent SPICE models for W-element transmission lines, inductors and MIM capacitors from GDSII layouts.

CLEVER is a physics-based RC extractor that uses GDSII mask data and process information to create a realistic 3D structure for MEMS, advanced CMOS, TFT, Memory cells, etc., using its built-in etch/deposit processor and optolithographical simulator. CLEVER back annotates extracted RCs into SPICE netlist.

STELLAR fills the size gap between typical small cell field solvers and full chip extractors. STELLAR uses a new highly efficient fictitious domain field solver to characterize cells containing tens of thousands of active elements, providing the physics-based accuracy of a field solver with the cell size capability of a full chip extractor.

DIGITAL CAD

SILOS AccuCell AccuCore HyperFault CatalystAD CatalystDA Spider

SILOS is an easy-to-use IEEE-1364-2001 compliant Verilog simulator used by leading IC designers. An industry standard since 1986, its powerful interactive debugging features provide today’s most productive design environment for FPGA, PLD, ASIC and custom digital designs.

AccuCell is an accurate, automated, fast and flexible software tool for characterizing and validating standard cell, I/O and custom cell libraries.

AccuCore performs timing characterization of multi-million device circuits with SmartSpice accuracy and performs block and full-chip Static Timing Analysis (STA) on multi-million gate designs.

HyperFault is a Verilog IEEE-1364-2001 compliant fault simulator that analyzes test vectors’ ability to detect faults. Supports mixed levels of gate, behavioral, and switch with SDF timing.

CatalystAD is the premier tool for converting transistor-level designs into verilog gate-level representations with applications in microprocessor, DSP, graphics and high-speed communication markets.

CatalystDA is a software program that translates a structural Verilog netlist into equivalent SPICE format netlist to be used for layout verification or SPICE simulation.

Experimental Skills:

Thin film deposition using sol gel process, Vacuum coating technique, Measurements using probe stations and device (pn junction, Schottky diodes, MOS capacitor, BJTs, FETs, MOSFETS, OPDs, OTFTs) characterization using HP semiconductor analyzer. Hall measurement, LCR meter etc.

Clean room techniques: Photo-lithography; Resist Spinning and Developing; Etching (Wet and Dry)

Thin film Deposition Equipment: Thermal Chemical Vapor Deposition System; Sputtering System,Ellipsometry.

Characterization Equipment:Scanning Electron Microscopy, Transmission Electron Microscopy, EDS, Atomic Force Microscopy and FTIR, Photoluminescence Spectroscopy, X-ray diffraction analysis (XRD), Electrochemical Characterization.

Fellowships / Awards / Prizes / Certificates etc.: