Physics-Based Modeling of Thermal Mismatch
and Crystal Anisotropy Effects
in Copper Vias and Metal Interconnects
Thermal mismatch stress, Anisotropic elasticity,
Microstructure-dependent deformation, Thermo-mechanical reliability
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Thermal cooling and crystal-level anisotropy influence stress evolution in copper interconnects and vias embedded in dielectric layers on silicon substrates.
The Financial Times Limited 2026
Modern semiconductor devices contain complex networks of copper interconnects embedded in dielectric layers above a silicon wafer.
During fabrication, the structure experiences thermal cycles from elevated processing temperatures to room temperature.
Because copper, silicon, and dielectric materials have very different thermal expansion coefficients, cooling induces internal stresses inside the metal wiring network.
These stresses can influence:
reliability
electromigration
interface failure
microstructure evolution.
Copper is a crystalline metal with cubic symmetry.
Individual grains exhibit anisotropic elastic behavior, meaning the stiffness depends on crystal orientation.
Therefore:
• different grains deform differently
• cooling mismatch generates heterogeneous stresses
• stress concentrations may increase near grain boundaries.
Physics-based modeling provides insight into
how microstructure, geometry, and thermal loading interact to determine
stress evolution in semiconductor interconnect systems.
These thermo-mechanical stresses are critical for the reliability of advanced semiconductor technologies used in high-performance computing, AI accelerators, and mobile processors.
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