Lab1: Introduction
In this Lab, you will be introduced to XILINX® ISE WebPACK schematic capture and simulation tools. A number of design experiments both combinational and sequential circuits in this laboratory course will be done using this computer aided design (CAD) tool.
Lab 2: Analysis of Logic circuits
Analyse the given circuit to obtain the logic equation. Apply all the possible combinations of the input variables and find the truth table. Use the Xilinx schematic capture and simulation tools to enter and simulate the circuits. Be sure to add I/O markers to both inputs and outputs (and be sure to change the output signals to output). Drive the circuit simulation with all possible combinations of inputs. Print and submit a copy of the schematic and simulation waveform files.
Lab 3: Synthsis of Logic circuit
In this lab, you will synthesise and implement a circuit that will accept any two of the four basic blood types as input and indicate of a blood transfusion is possible or not.
Lab 4:Design of one bit half adder & full adder and n bit binary ripple carry adder
A half adder has two binary inputs say, A and B and two binary outputs i.e S, sum bit and C, carry bit. Implement a half adder and also simulate using Xilinx schematic entry tools and verify your design with timing diagram results.
A full adder has three binary inputs say, A, B and C and two binary outputs i.e S, sum bit and C, carry bit. Implement a full adder and also simulate using Xilinx schematic entry tools and verify your design with your timing diagram results.
Design and simulate a two bit adder using Xilinx schematic entry tools. Let the two binary numbers to be added be represented by A1A0 and B1B0 and the resulting number be CS1S0 where S1S0 is the sum and C is the carry bit. With an appropriate example, illustrate the two bit addition with your timing diagram. Discuss how you can expand the circuit to design 4 bit adder, 8 bit adder, 16 bit adder etc. Illustrate it with a simulation result of 4 bit or 8 bit adder.
Lab. 5: Design of Adder-Subtractor logic circuit
Design a logic circuit that will perform both addition and subtraction using binary adder. You can use 74LS83 which is a 4 bit binary adder and other gates. The circuit must accept two 4 bit numbers (A3A2A1A0 and B3B2B1B0) and a control signal M, the input of which must determine the addition or subtraction operation. The subtraction must be performed using 2’s complement method. Also the circuit must give the carry output and indicate an overflow. With appropriate examples, illustrate the functionality with timing diagram. If the two numbers are signed numbers, your circuit using 74LS83 may not indicate overflow correctly. Discuss how you can implement an Adder-Subtractor circuit that detects overflow if the two numbers are signed numbers and draw the diagram of your new design.
Lab 6: In this lab you will extend the experiment you did in Lab 5. Design a BCD to seven segment decoder which will drive a seven segment display. Draw a neat truth table and the circuit. Using 74LS83 binary adder, set up to perform the addition of two 4bit unsigned numbers. Now interface with a BCD to seven segment decoder to display your results using a seven segment display. If the sum is greater than 9, the circuit is no longer works correctly. Can you think how you can modify the circuit so that a 4 bit addition results are displayed correctly. You may modify the circuit in anyway so that your results are displayed correctly in decimal.
Lab 7: Design a D latch with enable input. Also simulate and submit the timing diagram for D and enable/clock inputs waveforms shown below. Connect two D latch in master-slave configuration to realize an edge trigger D flip flop. Simulate and submit the timing diagram for the same D and clock inputs waveforms as above. Compare the two timing diagrams and give your comments. Now, configure your master-slave D flip flop as T flip flop which toggles with the clock input and get your outputs checked. Also simulate and submit your timing diagrams.
Lab 8 : Design of Synchronous and Asynchronous counter
Lab 9 : Design of a four bit Jhonson Counter. (the outputs of the flip flops are decoded to generate the eight timing signals)
Lab 10: Design of four bit bidirectional shift register
Lab 11: Introduction to FPGA and implementation of logic circuits on FPGA