Built-In Self-Test of High Speed Analog-to-Digital Converters (ADC BIST)

Introduction

This page gives an overview of the ADC BIST project started in November 2009 and completed in November 2013 (final results might be found at this link). The main problem addressed by this project was the investigation of an innovative solution for a feasible, reliable, and low cost test for high speed and moderate resolution analog-to-digital converters (ADCs). The achieved solution uses a built-in self-test (BIST) approach, which relies on two synchronized, small area phase-locked loops (PLLs) to generate high frequency signals for clock and analog input, and used to assess the dynamic performance of the ADC under test coherently. Using this approach, only an external, low frequency reference clock is needed (e.g., an inexpensive crystal oscillator). The output of the ADC under test may be processed on-chip, e.g., using optimized fast Fourier transform algorithms, by reusing the digital signal processing (DSP) resources available in a system-on-chip environment (assuming this is the application scenario). In the results presented next, however, the digital signal processing is made off-chip, in MATLAB. The project was supported in part by a PhD grant (reference SFRH/BD/62568/2009) from the Fundação para a Ciência e a Tecnologia, Portugal.

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Functional block diagram

The proposed BIST concept was fully integrated on-chip, except the digital signal processor. The integrated circuit is composed of three major building blocks: an analog-to-digital converter and two phase-locked loops. The analog-to-digital converter is the device under test (DUT), and the phase-locked loops generate the test stimuli. Some digital counters, controlled externally, are used to configure the dividers and voltage-controlled oscillators (discrete tuning) of both PLLs, as well as to select one of the three test modes: i) ADC stimulated with external analog input and clock (this mode assesses the performance of the ADC in standalone); ii) ADC stimulated with external analog input and internal clock; and iii) ADC stimulated with internal analog input and clock (this mode assesses the performance of the whole system, i.e., ADC + BIST).

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Printed circuit board design and fabrication

The fabricated integrated circuits are wire bonded directly onto printed circuit boards (PCBs) using chip-on-board technology. The PCB design was done in EAGLE software version 6.1.0 for Windows, Professional Edition. All files used in the design may be download here. After extracting the eagle_files.zip file you will get:

- A folder named eagle_wd: It is the working directory, which contains the printed circuit board schematic and layout designed in EAGLE.

- A file named my-library.lbr. It is a custom library with parts not available in the standard EAGLE libraries. Cut & paste this file into <your_eagle_install_path>/lbr.

- A file named eC_6Layer_PClass6_BaseCopperO18-I35_eCDefault.dru. It is a design rule check file provided by the printed circuit board manufacturer (in this case Eurocircuits, see more below). Cut & paste this file into <your_eagle_install_path>/dru.

The board design was based/inspired on the evaluation board of AD9484 (click here for details), which is one of the fastest analog-to-digital converters from Analog Devices at the time of this writing (Aug. 2013).

The fabrication of the printed circuit board was performed by Eurocircuits, Belgium. A standard 6-layer technology is used and the board has dimensions of 100 mm x 100 mm x 1.55 mm. The outer and inner layers copper foils are 18 um and 35 um, respectively, and the minimum outer/inner layer track width/spacing is 150 um. The surface finish is electroless gold over nickel (only at copper exposed by the soldermask).

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Chip-on-board

The chip-on-board service, which entails die attach, wire bonding and encapsulation, was performed by Nanium S.A., Portugal. The adhesive for die attach is heat cured, electrically non-conductive, and has silica fillers. The wire bonding between the die bonding pads and the printed circuit board pads was executed with ball bonding process using gold wire of 23.5 um diameter. Electroless gold over nickel surface finishing was used on the printed circuit board pads. The silicon die and bond wires are glop top encapsulated using a heat cured, black-opaque, epoxy resin.

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Printed circuit board assembly

The printed circuit board favors surface-mount devices over through-hole ones in order to reduce the board size and cost. The complete list of devices used in the PCB, as populated by EAGLE software, is available here. Most of these components are readily available in any electronic components distributor, e.g., Digi-Key, Farnell, Mouser Electronics, etc. The material required to assemble at least five printed circuit boards, ordered at Digi-Key, Farnell and Mini-Circuits, is indicated below. Note that some components are ordered at a larger than required quantity to get a more decent price per unit.

- For order placed at Digi-Key click here (main order).

- For order placed at Farnell click here (banana sockets, spacers, screws).

- For order placed at Mini-Circuits click here (RF transformers).

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Test setup and key measured results

The test board is power with the Tektronix PS2521G programmable power supply, which delivers 4 V to the low dropout (LDO) regulators with adjustable output voltage on-board. The output voltage of these LDOs is adjusted with on-board trimmers. Another set of on-board trimmers is used to adjust the reference biasing currents. The external analog input, needed in test modes i) and ii) discussed previously, is provided by the Marconi Instruments 2041 10 kHz - 2.7 GHz signal generator. In order to remove the harmonics of the generated signal, this signal is band-pass filtered before being applied to the test board. The external clock signal, both for ADC clocking or for PLL clock reference, is provided by the Rohde & Schwarz SMB100A/SMB-B112 100 kHz - 12.75 MHz signal generator. The ADC output data are captured with Agilent 16702B/16715A 167 MHz state, 667 MHz timing, 2 MSa logic analyzer. These data are then read remotely with a personal computer and processed in MATLAB. A set of on-board push-button switches allows the configuration of the system and the desired test mode selection.

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Some measurement results for one of the evaluated die samples are shown below, for the three test modes discussed above. These graphs represent the output spectrum (512 points) of the ADC under test when the sampling frequency is 464.64 MS/s, the analog input frequency is 226.875 MHz, and the analog input amplitude is -2.5 dBFS (frequency axis is decimated by 15). The spectral components indicated by H<i> represent the ith harmonic (only dominant odd harmonics are highlighted), while those indicated by R<i>l,r represent the ith-order left/right reference spur caused by the PLLs. The TI component represents the gain/timing mismatch spur present in the two-channel time-interleaved ADC (the converter topology selected in this project). By analyzing these graphs and considering the graph of test mode i) as a "golden reference", we can say:

a) The most noticeable differences in test modes ii) and iii) with respect to test mode i) are the presence of reference spurs and an incremented phase noise (timing jitter). Despite of this, all spectra have a coherent representation, which avoids the use of any type of windowing and the associated shortcomings.

b) The reference spurs are stronger than those predicted during the design phase, but, since they happen at well-known frequency bins and assuming they do not overlap/mask the spectral components of interest, we can neglect their impact and still be able to assess the dynamic performance of the ADC under test.

c) As an example of this assessment, the 3rd harmonic magnitude of test mode iii) differs only by 6.9 dB from the baseline performance of test mode i). The 3rd harmonic nonlinearity, in this case, is limited by linearities of the voltage-controlled oscillator (VCO) of PLL IN and of the linear buffer that follows this VCO and drives the input of the ADC under test. As another example, the TI spur differs only by 2.2 dB. Hence, if we disregard the reference spurs, the spectrum of test mode iii) is a good representation of that of test mode i). In this situation, we can concisely say that the quality of the test stimuli generated by the proposed BIST scheme allows us to evaluate a high speed (e.g. 500 MS/s or higher) ADC with a spurious-free dynamic range (SFDR) of about 41.4 dB at Nyquist.

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