digitalcircuits2

Input begins by coming into the Code Checker from the Input and Setup panels. The Controller tells the Code Checker which digit, in the code sequence from the Setup panel, it needs to compare to the information from the Input Panel. The Code Checker compares the two values. If the code matches it sends a high value, called Correct, into the Controller. This changes the Controllers state and determines if the Code Checker is to move onto the next digit in the code sequence.

If the complete correct code is entered the Unlock signal is asserted high, and the system is reset to its initial state. If an incorrect code is entered the Controller sends an Error signal (asserted high) to the Sleeper. The Sleeper counts the error signals. Upon the entry of the third error the Controller is reset and receives a low to its Enable for three minutes. No new code can be compared during these three minutes. At the end of the three minutes the system is back in its initial state once more.

Figure- 2:

Section III The Input Panel Translator

The input panel consists of 5 buttons which each emit a pulse when pressed. The buttons are labeled left to right; 1 through 4 followed by Reset.

Figure- 3:

The input panel translator simply converts each of these pulses into a 2-bit binary code, which is needed to be able to be compared with the setup values (Figure 4). An enable is sent along with each 2-bit code to tell the Code Checker that an input is being received. The actual behavior of a button being pressed by a human cannot be exactly modeled in a test bench.

Figure- 4:

The enable is asserted high for one clock cycle and then returns low. This allows the Code Checker enough time to receive the input but eliminates the problem of repeated checks of the same value. The Input Panel Translator is a user-defined symbol.

Figure 5 shows the waveform for the Input Panel Translator simulation. The waveform simply shows that each pulse is translated into 2 bits denoted out[0] and out[1] and that the enable is asserted long enough for the value to be received each time input from the panel is received. The enable then goes low eliminating redundant checks in the Code Checker.

Figure– 5:

(click to enlarge)

Section IV The Code Checker & Setup Panel

The Code Checker, made from discrete parts, compares a 2-bit binary code from the Input Panel Translator to a 2-bit binary code from the setup panel. The setup panel consists of 16 DIP-switches, the first 14 are designated as the code sequence and the last two are reserved for the code length. (See Figure-6)

Figure- 6:

Figure- 7: (click to enlarge)

Figure 7 shows the schematic for the Code Checker. Two 8:1 multiplexers are used to extract the 2 bits from the DIP-switches, which are then compared to the inputs from the Input Panel Translator. The select lines are tied to outputs from the Controller, which specifies the current state. This guarantees that the DIP-switches being checked correspond to the current position in the sequence. The circuit sends a high on result when the two codes are equal and a low otherwise.

Figure- 8: (click to enlarge)

Figure 8 shows the waveform for the Code Checker and setup panel. The test bench cycles through each state and checks each input. This accounts for all of the possible state and input configureurations. Note that for every state there is one and only one time that result is asserted high. The multiplexer state is shown to clarify that corresponding values are being compared. Result is set to high at the current time flag (set to 2581 ns). This shows that mux1 = 1 and the corresponding value from the Input Panel Translator (in[0]) is the same. Also, mux2 = 0 and the corresponding value (in[1]) is equal. At this point in the simulation the current state is 2. We see that the corresponding DIP-switches are 4 and 5, which have the same values as mux1 and mux2 respectively.

Section V The Controller

The Controller is a user-defined block, which supervises the signals produced by the Code Checker. It uses states to keep track of the number of correct digits entered. The Controller either sends an Unlock signal when the code is entered successfully or an error signal to the Sleeper that an incorrect digit has been entered. The Controller receives input from the setup panel to determine the length of the code.

The Controller receives results from the Code Checker. If the Code Checker sends a low the Controller evaluates it as an error. If a high signal is received, the Controller continues to the next state. The Controller outputs the current state so that the Code Checker knows the next value to be compared.

An enable e from the Sleeper is used to disable the Controller, for three minutes, if three errors are received. The reset, which resets the state back to zero and starts the sequence over, is received from the input panel. This reset also sets the Unlock and Incorrect signals to low. The Unlock signal goes high when the Controller has arrived at the correct number of true values. If the user sends an Incorrect value to the Code Checker, the Code Checker sends a low to the Controller which in turn sets the state back to 0 and relays the Incorrect signal high to the Sleeper unit.

The state graph (see Figure 9) and function tables (Appendix XXXXX Figure XXXX) show how the Controller reacts to all contingencies allowed by input. The state graph shows that both the outputs Incorrect and Unlock are mealy outputs, which rely on user input from the input panel. The Controller works successfully for all cases.

Figure- 9:

The waveform in Figure 10 shows that when the enable is high, and reset is low, the state increments each clock cycle that the Controller is receiving correct input values. If an incorrect value is entered the Incorrect-signal goes high and the state resets to zero. All changes are made, and the input is reevaluated, on the positive edge of the clock cycle.

Figure- 10: (click to enlarge)

Section VI The Sleeper

The purpose of the Sleeper circuit is to discourage the attempts of thieves from repeatedly entering random digits at the keypad and successfully opening the vehicle door. This discouragement is in the form of a three-minute lockdown time, in which no further attempts can be made at entering a correct code.

The Sleeper circuit is composed of two halves. The first half is a state machine that counts the number of incorrect errors entered from the keypad. The second half of the Sleeper is the 555-timer circuit, which disables the Control unit after three incorrect entries have been made.

The Sleeper’s state machine has two inputs and two outputs. The inputs are U for Unlock, and E for Error and both signals come from the Controller circuit. By their very nature the Error signal and Unlock signal will never be asserted high at the same time. The state machines outputs are Re, which resets both the Controller and the Code Checker; and Tr, which is a trigger for the timer circuit that makes it enter the designated three-minute sleep mode.

Figure– 11: (click to enlarge)

The Sleeper’s state machine has a total of four possible states represented by two binary digits (Figure -11). State zero represents zero entered incorrect attempts, and is the starting state for the machine. State one and two represent one and two incorrectly entered numbers, from the keypad, respectively. If the Error signal is asserted high, the state machine progresses through the states, in order from state zero to state two. In each of these progressions to the next state the Reset output will be asserted high as is shown in the Sleeper waveform (Figure 12) from 0-200ns.

Figure- 12: (click to enlarge)

As also can bee seen in the sleeper waveform (300- 400ns) while in state two, a high on the Error signal sends the state machine back to state zero and both the Reset and Trigger outputs are asserted high. The assertion of both outputs first resets the Controller and Code Checker, and then the sleep cycle starts. The transition from state two into the zero state, from an Error signal, is the only time that the Trigger output is asserted high. The sleep cycle lasts for 3 minutes and during this time the Controller cannot read any input from the Code Checker. When the cycle is over the states are ready to start their progression again (500-600ns). The last quarter of the Sleeper waveform shows that if the Unlock signal is asserted high from any given state, then Reset is asserted high on the output. Each of these possibilities is shown in the Sleeper’s truth tables in Figure 13.

Figure- 13:

The 555-timer used in the second half of the Sleeper is used to make a monostable circuit, by creating a single pulse for a set time length in response to a trigger. The output of the 555 is sent as an Enable to the Controller. The Controller requires the Enable to be high to work, but the 555 outputs a high signal when it wants the Enable to go low. To solve this problem the Enable signal is sent through an inverter before it reaches the Controller.

The time delay for the 555 is calculated using the equation:

T(s) = R

1.1 * C

Where T is time in seconds, C is capacitance in Farads, and R is resistance. For a three-minute sleep time our capacitance rating comes out at 1800µf, and our Resistance to 90K Ohms.

Figure- 14:

The 555’s trigger works off of a low signal, to convert our high Tr signal to a low pulse the Tr output is run into the base of a 3904 transistor. The transistor will connect Vcc to ground through a 10Kohm resistor. Between the resistor and the transistor is a connection to the input pin (#2) on the 555-timer (See Figure 14 and 15). As power is applied to the 3904’s base a drop in voltage will be detected on the 555’s input pin. This will cause the 1800µf capacitor to slowly charge, and the timer circuit will send a low to the Enable on the input of the Controller circuit. This process takes three-minute’s time. Once the time frame has elapsed the Enable is asserted high and additional attempts may be made at entering a correct code sequence.

Figure- 15: (click to enlarge)

Section VII Conclusion

The code length can be varied between four and seven digits long. The code has a total of 21,760 combinations to prevent guessing the correct one. Only three incorrect digits may be entered with each try at entering the correct code. The system is inoperable for 3 minutes, to deter thieves, with every third incorrect entry attempt. With this system a vehicle can remain secure, and entry to the car can be made without the keys, so long as the user has the correct numerical code.