Digital Design with the Verilog HDL

This course emphasizes the use of FPGAs and Verilog HDL to design and implement combinational and sequential circuits. In addition, students use various software tools to model, simulate, and implement digital circuits to solve specific problems. The course projects are intended to build the students’ ability to design, implement, simulate, and verify operations of simple designs.

Course learning outcomes: Students who complete this course will be able to:

- conduct experiments for specific digital circuits and analyze simulation results;

- design and use Verilog HDL to describe combinational and sequential digital circuits;

- design finite state machines for specific problems and use Verilog to implement the FSMs;

- use Electronic Design Automation tools to simulate and implement digital systems.

Students can download slides from here or from the BKeL site

1. Chapter 0: Introduction (slide)

2. Chapter 1: Digital Design: a Review (slide)

3. Chapter 2: Introduction to Verilog - Structural Model (slide)

4. Chapter 3: Hierarchy & Simulation in Verilog (slide)

5. Chapter 4: Continuous Assignment (slide)

6. Chapter 5: Behavioral Model in Verilog (slide_part1, slide_part2)

7. Chapter 6: Finite State Machine (slide_part1, slide_part2)

8. Chapter 7: Parameters, Task, and Function in Verilog (slide)

9. Chapter 8: Datapath and Controller (slide)

To download the following files, you need to log in with your HCMUT account if required.

Modelsim 16 simulation tool (Window): download

Modelsim simulation tool (Linux): download

Installing Quartus 16.1 Lite guide (for both Window and Linux): download

Module D-FF: download => structural counter module: download

Module 4-bit comparator Comp4Str: download