Publications

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List of published books/book chapters:

2015

• Cuong Pham-Quoc, "Hybrid Interconnect Design for Heterogeneous Hardware Accelerators", Publisher Delft University of Technology, ISBN 978-94-6186-448-2 (doi=10.4233/uuid:862e5b58-b9d1-462a-90b0-6f94a054632e)

2017

• Phạm Quốc Cường, "Kiến trúc Máy tính", Nhà xuất bản Đại học Quốc gia TPHCM, ISBN: 978-604-73-4662-2 (Cover&Outline)

• Thoai Nam, Tran Khanh Dang, Tran Ngoc Thinh, Cuong Pham-Quoc, "Proceedings of AUN/SEED-Net Regional Conference on Computer and Information Engineering - RCCIE 2017", Vietnam National University - HCMC Press, ISBN: 978-604-73-5687-4

List of selected published papers/articles:

2023

• Cuong Pham-Quoc, Bao THQ, Thinh TN. "FPGA/AI-Powered Architecture for Anomaly Network Intrusion Detection Systems," Electronics. 2023; 12(3):668 (doi=10.3390/electronics12030668) (SCIE/Q2)

• B. K. Do-Nguyen, Cuong Pham-Quoc, N. -T. Tran, C. -K. Pham and T. -T. Hoang, "Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor," in IEEE Access, vol. 11, pp. 4879-4894, 2023, (doi=10.1109/ACCESS.2023.3236406), (SCIE/Q1)

• Ngo, D.-M.; Lightbody, D.; Temko, A.; Cuong Pham-Quoc; Tran, N.-T.; Murphy, C.C.; Popovici, E. "HH-NIDS: Heterogeneous Hardware-Based Network Intrusion Detection Framework for IoT Security," Future Internet 2023, 15, 9. (doi=10.3390/fi15010009) (ESCI/Q2)

2022

• Cuong Pham-Quoc, Nguyen, XQ., Thinh, T.N., "Towards An FPGA-targeted Hardware/Software Co-design Framework for CNN-based Edge Computing," Mobile Netw Appl 27, 2024–2035 (2022). (doi=10.1007/s11036-022-01985-9) (SCIE/Q2)

• B Kieu-Do-Nguyen, Cuong Pham-Quoc, NT Tran, CK Pham, TT Hoang, "Low-Cost Area-Efficient FPGA-Based Multi-Functional ECDSA/EdDSA," in Cryptography 6 (2), 25 (doi=10.3390/cryptography6020025) - (ESCI/Scopus Q2)

• Vu Tuan Anh, Cuong Pham-Quoc, "Building a smart traffic light system based on Internet of Things using pi‐calculus," in Concurrency Computat Pract Exper. 2022; 34( 10):e6731. (doi=10.1002/cpe.6731) - (SCIE/Scopus Q2)

2021

• Tran Ngoc Thinh, Bao Tran H.Q., Duc-Minh Ngo, Cuong Pham-Quoc, "High-performance anomaly intrusion detection system with ensemble neural networks on reconfigurable hardware," in Concurrency Computat Pract Exper. 2021;e6370 (doi=10.1002/cpe.6370) - (SCIE/Scopus Q2)

• Binh Kieu-Do-Nguyen, Cuong Pham-Quoc, and Cong-Kha Pham, "High-Performance FPGA-Based BWA-MEM Accelerator," International Journal of Machine Learning and Computing vol. 11, no. 3, pp. 256-261, 2021 (doi=10.18178/ijmlc. 2021.11.3.1044)

2020

• Duc-Minh Ngo, Cuong Pham-Quoc, Tran Ngoc Thinh, "Heterogeneous Hardware-based Network Intrusion Detection System with Multiple Approaches for SDN," in Mobile Networks and Applications, page 1178–1192, Vol. 25, Issue 3, June - 2020, (doi=10.1007/s11036-019-01437-x) (SCIE/Scopus Q2)

• Binh Kieu-Do, Cuong Pham-Quoc, Cong-Kha Pham, "Hardware-assisted High-performance DNA Alignment System," 2020 5th International Conference on Intelligent Information Technology (ICIIT 2020), 2020, Hanoi - Việt Nam (doi=10.1145/3385209.3385223)

• Binh Kieu-Do, Cuong Pham-Quoc, Cong-Kha Pham, "Heterogeneous Hardware-assisted Parallel Processing for BWA-MEM DNA Alignment," in The 2020 RIVF International Conference of Computing and Communication Technologies, October 14-15, 2020, Ho Chi Minh City, Vietnam (doi=10.1109/RIVF48685.2020.9140768)

2019

• Cuong Pham-Quoc, Binh Kieu-Do, Tran Ngoc Thinh, "A high-performance FPGA-based BWA-MEM DNA sequence alignment," in Concurrency Computation: Practice and Experience. vol. 33, issue 2, first online May-2019;e5328. (doi=10.1002/cpe.5328) (SCIE/Scopus Q2)

• Cuong Pham-Quoc, Duc-Minh Ngo, Tran Ngoc Thinh, "HPOFS: A High Performance and Secured OpenFlow Switch Architecture for FPGA," in Advances in Electrical and Computer Engineering, vol.19, no.3, pp.19-28, 2019, (doi=10.4316/AECE.2019.03003) (SCIE/Scopus Q3)

• Cuong Pham-Quoc, "Design Framework for FPGA-based Hardware Accelerators with Heterogeneous Interconnect," 2019 6th NAFOSTED Conference on Information and Computer Science (NICS), 12-13 Dec. 2019, Hanoi, Vietnam (doi=10.1109/NICS48868.2019.9023825)

2018

• Duc-Minh Ngo, Cuong Pham-Quoc, Tran Ngoc Thinh "An Efficient High-Throughput and Low-Latency SYN Flood Defender for High-Speed Networks," Security and Communication Networks, vol. 2018, Article ID 9562801, 14 pages, 2018. (doi=10.1155/2018/9562801) (SCIE/Scopus Q2)

• Cuong Pham-Quoc, Binh Kieu-Do-Nguyen, and Tran Ngoc Thinh, "An FPGA-based Seed Extension IP core for BWA-MEM DNA Alignment," Advanced Computing and Applications (ACOMP), 2018, Ho Chi Minh - Việt Nam (doi=10.1109/ACOMP.2018.00009)

• Binh Tran-Thanh, Cuong Pham-Quoc, and Tran Ngoc Thinh, "OpenFlow Switches with Integrated Tiny NIDS to Mitigate Network Attacks," International Journal of Computer Engineering and Information Technology, Vol. 10, No. 6, 85–91, 2018 (online)

2017

• Cuong Pham-Quoc, Binh Tran-Thanh, Tran Ngoc Thinh, "Scalable FPGA-based Floating-Point Gaussian Filtering Architecture," International Conference on Advanced Computing and Applications (ACOMP), 29 Nov - 1 Dec 2017, Ho Chi Minh City, Vietnam (doi=10.1109/ACOMP.2017.27)

• Cuong Pham-Quoc, Binh Kieu-Do, Anh-Vu Dinh-Duc, "BKVex: an Adaptable VLIW Processor and Design Framework for Reconfigurable Computing Platforms," International Conference on Advanced Computing and Applications (ACOMP), 29 Nov - 1 Dec 2017, Ho Chi Minh City, Vietnam (doi=10.1109/ACOMP.2017.24)

• Duy Le Nguyen Khanh, Cuong Pham-Quoc, and Le Tan Quan, "Computer and Network Forensics: Technology challenges and research questions in Vietnam," AUN/SEED-Net Regional Conference on Computer and Information Engineering, 2017, Ho Chi Minh City, Vietnam

• Cuong Pham-Quoc, Tran Ngoc Thinh, "An Efficient Runtime Adaptable Floating-Point Gaussian Filtering Core," the 4rd NAFOSTED Conference on Information and Computer Science, 24-25 Nov 2017, Hanoi, Vietnam (doi=10.1109/NAFOSTED.2017.8108061)

• Cuong Pham-Quoc, Binh Kieu-Do, Anh-Vu Dinh-Duc, "Adaptable VLIW Processor: the Reconfigurable Technology Approach," The 10th International Conference on Advanced Technologies for Communication (ATC), 18-20 October 2017, Quy Nhon, Vietnam (doi=10.1109/ATC.2017.8167600)

• Biet Nguyen-Hoang, Binh Tran-Thanh, Cuong Pham-Quoc, Nguyen Quoc Tuan, Tran Ngoc Thinh, "A Novel High-Speed Architecture for Integrating Multiple DDoS Countermeasure Mechanisms Using Reconfigurable Hardware," Journal of Telecommunication, Electronic and Computer Engineering (JTEC), Volume 9, Issue 2-4, 2017, Page 41-46, ISSN:2180-1843 (Scopus Q4)

2016

• Cuong Pham-Quoc, Biet Nguyen, Tran Ngoc Thinh, "FPGA-based Multicore Architecture for Integrating Multiple DDoS Defense Mechanisms," ACM SIGARCH Computer Architecture News, Volume 44 Issue 4, September 2016, ISSN:0163-5964 (doi=10.1145/3039902.3039906)

• Bao Ho, Cuong Pham-Quoc, Tran Ngoc Thinh and Nam Thoai, "A Secured OpenFlow-based Switch Architecture," International Conference on Advanced Computing and Applications (ACOMP 2016), 23-25 November 2016, Can Tho, Vietnam (doi=10.1109/ACOMP.2016.021)

•  Bao Ho, Quoc Nguyen, Cuong Pham-Quoc and Tran Ngoc Thinh, "Secured-OFS: A Novel OpenFlow Switch Architecture with Integrated Security Functions," The Advanced of International Conference on Advances in Information and Communication Technology (ICTA2016), 12-13  December 2016, Thai Nguyen, Vietnam (doi=10.1007/978-3-319-49073-1_57)

2015

• Cuong Pham-Quoc, Imran Ashraf, Zaid Al-Ars, Koen Bertels, "Heterogeneous Hardware Accelerator with Hybrid Interconnect: an Automated Design Approach," International Conference on Advanced Computing and Applications (ACOMP 2015), 23-25 November 2015, Ho Chi Minh City, Vietnam (doi=10.1109/ACOMP.2015.26)

• Tran Ngoc Thinh, Cuong Pham-Quoc, Biet Nguyen-Hoang, Quoc Nguyen-Bao, Nguyen Quoc Tuan, "FPGA-based Multiple DDoS Countermeasure Mechanisms System Using Partial Dynamic Reconfiguration," REV Journal on Electronics and Communications, ISSN: 1859-378X, 5, July-Dec, 2015 (doi=10.21553/rev-jec.137)

2014

• R. Nane, V.M. Sima, Cuong Pham-Quoc, F Goncalves, K.L.M. Bertels, "High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain," 12th IEEE International Conference on Embedded and Ubiquitous Computing (EUC 2014), 26-28 August 2014, Milan, Italy (doi=10.1109/EUC.2014.28 )

• Cuong Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, "Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling," 28th International Parallel & Distributed Processing Symposium Workshops (IPDPSW 2014), 19-23 May 2014, Phoenix, USA (doi=10.1109/IPDPSW.2014.21)

2013

• Cuong Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, "Heterogeneous Hardware Accelerator Architecture for Streaming Image Processing," International Conference on Advanced Technologies for Communications (ATC 2013), 16-18 October 2013, Ho Chi Minh City, Vietnam (doi=10.1109/ATC.2013.6698140)

• Cuong Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, "Heterogeneous Hardware Accelerators Interconnect: An Overview," NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2013), 25-27 June 2013, Torino, Italy (doi=10.1109/AHS.2013.6604245)

• Cuong Pham-Quoc, J. Heisswolf, S. Wenner, Z. Al-Ars, J.A. Becker, K.L.M. Bertels, "Hybrid Interconnect Design for Heterogeneous Hardware Accelerators," Design, Automation & Test in Europe Conference & Exhibition (DATE 2013), 18-22 March 2013, Grenoble, France (doi=10.7873/DATE.2013.178)

2012

• Cuong Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, "Rule-Based Data Communication Optimization Using Quantitative Communication Profiling," International Conference on Field-Programmable Technology (FPT 2012), 10-12 December 2012, Seoul, Korea (doi=10.1109/FPT.2012.6412119)

• Cuong Pham-Quoc, Z. Al-Ars, K.L.M. Bertels, "A Heuristic-based Communication-aware Hardware Optimization Approach in Heterogeneous Multicore Systems," International Conference on ReConFigurable Computing and FPGAs (ReConFig 2012), 5-7 December 2012, Cancun, Mexico (doi=10.1109/ReConFig.2012.6416720)

2011

• Cuong Pham-Quoc, Dinh-Duc A.V., "Automatic Generation of Area Constraints for FPGA Implementation," 2011 IEEE 3rd International Conference on Communication Software and Networks, April 1-3, 2011, Bali, Indonesia (doi=10.1109/ICCSN.2011.6014937)

2010

• Cuong Pham-Quoc, Dinh-Duc A.V., "Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA," the 5th IEEE International Symposium on Electronic Design, Test & Applications (DELTA 2010), Ho Chi Minh, Vietnam, January 13-15, 2010, ISBN 978-0-7695-3978-2, pp. 289-292 (doi=10.1109/DELTA.2010.40)

2009

• Cuong Pham-Quoc and Dinh-Duc A.V., "New Approaches to Design Asynchronous Circuits on FPGAs," the 2nd International Conferences on Advanced Technologies for Communications (ATC 2009), Haiphong, Vietnam, October 12-14, 2009, ISBN 978-1-4244-5139-5, pp. 63-67 (doi=10.1109/ATC.2009.5349341)

2007

• Cuong Pham-Quoc, Nguyen-Vu T.N., Dinh-Duc A.V., and Pham H.A. "Placement and Routing Algorithms for Asynchronous Logic Circuits," Special Issue of the Science and Technology Development Journal, Vol. 10, (13) 2007, VNU-HCM Press, ISSN 1859-0128, pp. 79-87.