Publications
CONFERENCES
2023
C. Augustine, P. Meinerzhagen, W. Lim, A. Veerabathini, M. Bright, K. Mojjada, J. Tschanz, M. Khellah, V. De, "A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS ", VLSI Circuit Symposium 2023.
2021
C. Augustine, A. Afzal, U. Misgar, A. Owahid, A. Raman, K. Subramanian, F. Merchant, J. W. Tschanz, M. M. Khellah, "All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP ", VLSI Circuit Symposium 2021.
X. Wang, C. Augustine, E. Nurvitadhi, R. Iyer, L. Zhao and R. Das, "Cache Compression with Efficient in-SRAM Data Comparison", NAS 2021.
X. Wang, V. Goyal, J. Yu, V. Bertacco, A. Boutros, E. Nurvitadhi, C. Augustine, R. Iyer and R. Das, "Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs", International Symposium on Field-Programmable Custom Computing Machines, 2021.
2020
C. Augustine, S. Paul, T. Majumder, J. W. Tschanz, M. Khellah, V. De, "2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads", VLSI Circuit Symposium 2020.
S. Paul, T. Majumder, C. Augustine, A. F. Malavasi, S. Usirikayala, R. Kumar, J. Kollikunnel, S. Chhabra, S. Yada, M. L. Barajas, C. Ornelas, D. Lake, M. M. Khellah, J. Tschanz, V. De, "A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit", VLSI Circuit Symposium 2020.
J. P. Kulkarni, A. Malavasi, C. Augustine, C. Tokunaga, J. Tschanz, M. M. Khellah, V. De, "Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-bitcell SRAM in 10nm FinFET CMOS", VLSI Circuit Symposium 2020.
S.Bang, W. Lim, C. Augustine, A. Malavasi, M. Khellah, J. Tschanz, V. De, "A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS", International Solid State Circuit Conference (ISSCC) 2020.
2019
Z. Ahmed, H. Krishnamurthy, C. Augustine, S. Weng, X. Liu, K. Ravichandran, J. Tschanz, V. De, "A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response", VLSI Circuit Symposium 2019.
X. Wang, J. Yu, C. Augustine, R. Iyer, R. Das, “Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks,” Int’l Symposium on High Performance Computer Architecture (HPCA 2019).
2018
P. Meinerzhagen, et. al., "An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS", International Solid State Circuit Conference (ISSCC) 2018.
2016
C. Augustine, C. Tokunaga, A. Malavasi, A. Raychowdhury, M. Khellah, J. Tschanz, V. De, "Characterization of PVT Variation & Aging Induced Hold Time Margins of Flip-Flop Arrays at NTV in 22nm Tri-Gate CMOS", International Electron Devices Meeting (IEDM) 2016
S. Sheik, S. Paul, C. Augustine, C. Kothapalli, M. Khellah, G. Cauwenberghs "Membrane-dependent Neuromorphic Learning Rule for Unsupervised Spike Pattern Detection", BioCAS 2016.
B. Pedroni, S. Sheik, S. Joshi, G. Detorakis, S. Paul, C. Augustine, E. Neftci, and G. Cauwenberghs, "Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity", BioCAS 2016
A. A. Sharma, Y. Kesim, M. Shulaker, C. Kuo, C. Augustine, H.S.-P. Wong, S. Mitra, M.Skowronski, J.A. Bain, J.A. Weldon, "Low-Power, High-Performance S-NDR Oscillators for Stereo (3D) Vision using Directly-Coupled Oscillator Networks", VLSI Technology Symposium, 2016.
S. Sheik, S. Paul, C. Augustine, C. Kothapalli, M. Khellah, G. Cauwenberghs, E. Neftci, "Synaptic Sampling in Hardware Spiking Neural Networks", ISCAS 2016.
M. Cho, S. Kim, C. Tokunaga, C. Augustine, J. Kulkarni, K. Ravichandran, J. Tschanz, M. Khellah, V. De, "Post-Silicon Voltage Guard-Band Reduction in a 22nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating", International Solid State Circuit Conference (ISSCC) 2016.
2015
A.A. Sharma, T.C. Jackson, M. Schulaker, C. Kuo, C. Augustine, J.A. Bain, H.S.-P Wong, S. Mitra, L.T. Pileggi, J.A. Weldon, "High Performance, Integrated 1T1R Oxide-based Oscillator – Stack Engineering for Low-Power operation in neural network applications," VLSI Technology Symposium, 2015.
J. P. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen Jr, C. Augustine, J. Tschanz, V. De, "A 409GOPS/W Adaptive and Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging", International Solid State Circuit Conference (ISSCC), 2015.
S. T. Kim, Y-C. Shih, K. Mazumdar, R. Jain, J. F. Ryan, C. Tokunaga, C. Augustine, J. P. Kulkarni, K. Ravichandran, J. W. Tschanz, "Enabling Wide Autonomous DVFS in a 22nm Graphics Execution Core Using a Digitally Controlled Hybrid LDO/Switched-Capacitor VR with Fast Droop Mitigation", International Solid State Circuit Conference (ISSCC), 2015.
2014
C. Tokunaga, J. Ryan, C. Augustine, J. Kulkarni, Y. Shih, S. Kim, R. Jain, K. Bowman, A. Raychowdury, M. Khellah, J. Tschanz and V. De, "A Graphics Execution Core in 22nm CMOS Featuring Adaptive Clocking, Selective Boosting and State-Retentive Sleep", International Solid State Circuit Conference (ISSCC), 2014.
S. Paul, J. Zamora, C. Lo, C. Augustine, L. Zhao, “A Low-Power Neural Network Using Approximate Computing”, Workshop on SoCs, Heterogeneous Architectures and Workloads, 2014.
2013
C. Chen, K. Bowman, C. Augustine, Z. Zhang, and J. Tschanz, "Minimum Supply Voltage for Sequential Logic Circuits in a 22nm Technology", International Symposium on Low Power Electronic Design (ISLPED), 2013.
2012
M. Sharad, C. Augustine, and K. Roy,, “Boolean and Non-Boolean Computation with Spin Devices”, International Electron Devices Meeting (IEDM) 2012.
C. Augustine, N. N. Mojumder, X. Fong, H. Choday, S. P. Park and K. Roy, “Spin-Transfer Torque MRAMs for Future Low Power Memories: Perspective and Prospective”, International Conference on Microelectronics (MIEL), 2012.
R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy and A. Raghunathan “TapeCache: A High Density, Energy Efficient Cache Based on Domain Wall Memory”, International Symposium on Low Power Electronic Design (ISLPED), 2012 (Best Paper Award).
M. Sharad, G. Panagopoulos, C. Augustine, and K. Roy, "Nano-Magnets and Metals Put to Neurmorphic Computation Can Relax the Burden on CMOS," DAC 2012.
M. Sharad, C. Augustine, G. Panagopoulos, A. Sarkar, and K. Roy, "Low Power, Programmable Neural Network Hardware Using Spin Devices," International Joint Conference on Neural Networks (IJCNN), 2012.
G. Panagopoulos, C. Augustine, and K. Roy, “A Framework for Simulating Hybrid MTJ/CMOS Circuits: Atoms to System Approach”, IEEE DATE 2012.
G. Panagopoulos, C. Augustine, X. Fong and K. Roy, “Exploring Variability and Reliability of Multi-Level STT-MRAM Cells”, IEEE DRC 2012.
M. Sharad, G. Panagopoulos, C. Augustine, and K. Roy, “NLSTT-MRAM: Robust Spin Transfer Torque MRAM using Non-Local Spin Injection for Write”, IEEE DRC 2012.
M. Sharad, G. Panagopoulos, C. Augustine, and K. Roy, “Ultra Low Energy Analog Image Processing Using Spin Based Neurons”, IEEE NANOARCH, 2012.
2011
C. Augustine, A. Raychowdhury, B. Behin-Aein, S. Srinivasan, J. Tschanz, Vivek De, and K. Roy, “Numerical Analysis of Domain Wall Propagation for Dense Memory Arrays”, International Electron Devices Meeting (IEDM) 2011.
A. Raychowdhury, D. Somsekhar, C. Augustine, J. Tschanz, K. Roy, V. De, "1T-1STT MTJ Memory Arrays for Embedded Applications”, Non-Volatile Memories Workshop (NVMW), 2011.
A. Raychowdhury, C. Augustine, D. Somsekhar, J. Tschanz, K. Roy, and V. De, “Numerical Analysis of a Novel MTJ Stack for High Readability and Writability”, European Solid-State Device Research Conference (ESSDERC), 2011.
C. Augustine, G. Panagopoulos, B. Behin-Aein, S. Srinivasan, A. Sarkar, and K. Roy, “Low-Power Functionality Enhanced Computation Architecture Using Spin-Based Devices”, IEEE NANOARCH, 2011.
V. Rangha, V. Kumar, C. Augustine, A. Raghunathan and K. Roy, “Energy Efficient Many-core Processor for Recognition and Mining using Spin-based Memory”, IEEE NANOARCH, 2011.
G. Panagopoulos, C. Augustine, and K. Roy, “Modeling of Soft Breakdown Induced Time Dependent STT-MRAM Performance Degradation”, IEEE DRC, 2011.
M. A. Alam, K. Roy, C. Augustine, “Reliability- and Process-Variation Aware Design of Integrated Circuits – A Broader Perspective”, IEEE International Reliability Physics Symposium (IRPS), 2011.
X. Fong, S. K. Gupta, N. N. Mojumder, S. H. Choday, C. Augustine, and K. Roy, “KNACK: a hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells,” SISPAD 2011.
2010
C. Augustine, A. Raychowdhury, D. Somsekhar, J. Tschanz, K. Roy, Vivek De, “Numerical Analysis of Typical STT-MTJ Stacks for 1T-1R Memory Arrays”, International Electron Devices Meeting (IEDM) 2010.
F. Moradi, C. Augustine, A. Goel, G. Karakonstantis, D. Wisland, H. Mahmoodi, K. Roy, "Data-Dependent Sense-Amplifier Flip Flop for Low Power Applications", IEEE International Custom Integrated Circuit Conference (CICC), 2010.
Y. Gao, C. Augustine, D. E. Nikonov, K. Roy and M. Lundstrom, “Realistic Spin-FET Performance Assessment for Reconfigurable Logic Circuits,” VLSI Technology Symposium 2010.
G. Karakonstantis, C. Augustine and K. Roy, “Self-consistent NBTI degradation model and on-line system lifetime enhancement,” IEEE IOLTS, 2010.
N. N. Mojumder, C. Augustine, D. E. Nikonov and K. Roy, “Spin Torques Estimation and Magnetization Dynamics in Dual Barrier Resonant Tunneling Penta-Layer Magnetic Tunnel Junctions,” IEEE DRC, 2010.
N. N. Mojumder, C. Augustine and K. Roy, “Self-Consistent Micro-Magnetic Simulation and Benchmarking of Different Spin-Torque Driven Magnetic Tunnel Junctions (MTJs),” UGIM, 2010.
C. Augustine, X. Fong and K. Roy, “Dual Ferroelectric Capacitor Architecture and its Application to TAG RAM,” IEEE ICICDT, 2010.
2009
C. Augustine, X. Fong, B. Behin-Aein, K. Roy, “A Comprehensive Nano-magnet Based Logic Synthesis for Ultra-Low Power Digital Systems”, SRC TECHCON 2009 (Best Paper in Session Award).
C. Augustine, A. Raychowdhury, Y. Gao, M. Lundstrom, K. Roy, “A Device/Circuit Analysis Framework for Evaluation and Comparison of Charge Based Emerging Devices”, IEEE ISQED 2009 (Best Paper Nomination).
C. Augustine, B. Behin-Aein and K. Roy, “Nano-Magnet Based Ultra-Low Power Logic Design Using Non-Majority Gates”, IEEE-Nano, 2009.
C. Augustine, B. Behin-Aein, X. Fong, K. Roy, “A Design Methodology and Device/Circuit/Architecture Compatible Simulation Framework for Low-Power Magnetic Quantum Cellular Automata Systems”, IEEE ASP-DAC, 2009.
J. Kulkarni, C. Augustine, B. Jung, K. Roy, “Nano-Spiral Inductors for Low Power Digital Spintronic Circuits”, IEEE International Magnetic Conference, 2009.
2008
N. Banerjee, C. Augustine, K. Roy, “Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and its Application to Digital Signal Processing Systems”, IEEE DFT‟08.
J. Li, C. Augustine, S. Salahuddin. K. Roy, “Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) Array for Yield Enhancement”, IEEE DAC‟08.
A. Raychowdhury, C. Augustine, Y. Gao, M. Lundstrom, K. Roy, “Purdue Emerging Technology Evaluator (PETE): A Device/Circuit Analysis Framework for Comprehensive Assessment of Emerging Devices”, SRC TECHCON 2008.
JOURNALS
2022
C. Eckert, A. Subramaniyan, X. Wang, C. Augustine, R. Iyer, and R. Das, "Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks", IEEE Transcation on Computers, 2022.
2020
Z. Ahmed, H. Krishnamurthy, C. Augustine, S. Weng, X. Liu, K. Ravichandran, J. Tschanz, V. De, "A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response", Journal of Solid-State Circuits (JSSC), 2020.
2019
B. U. Pedroni, S. Joshi, S. Deiss, S. Sheik, G. Detorakis, S. Paul, C. Augustine, E. O Neftci, G. Cauwenberghs, "Memory-efficient Synaptic Connectivity for Spike-Timing-Dependent Plasticity ", Frontiers in Neuroscience, 2019.
2018
G. Detorakis, S. Sheik, C. Augustine, S. Paul, B. Umbria Pedroni, N. Dutt, J. L. Krichmar, G. Cauwenberghs, E. O. Neftci , “Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning”, Frontiers in Neuroscience, 2018.
P. Meinerzhagen, et al, " An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS", JSSC 2018.
2017
E. Neftci, C. Augustine, S. Paul, and G. Detorakis, "Event-Driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines", Frontiers in Neuroscience, 2017.
2016
M. Cho, S. T Kim, C. Tokunaga, C. Augustine, J. P. Kulkarni, K. Ravichandran, J. W Tschanz, M. Khellah, V. De "Postsilicon voltage guard-band reduction in a 22 nm graphics execution core using adaptive voltage scaling and dynamic power gating " Journal of Solid-State Circuits (JSSC), 2016.
2015
S. T. Kim, Y-C. Shih, K. Mazumdar, R. Jain, J. F. Ryan, C. Tokunaga, C. Augustine, J. P. Kulkarni, K. Ravichandran, J. W. Tschanz, M. Khellah, V. De "Enabling Wide Autonomous DVFS in a 22nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator" Journal of Solid-State Circuits (JSSC), 2015.
J. P. Kulkarni, C. Tokunaga, P. Aseron, T. Nguyen Jr, C. Augustine, J. Tschanz, V. De, "A 409GOPS/W Adaptive and Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging", Journal of Solid-State Circuits (JSSC), 2015.
2014
R. Venkatesan, V. Kozhikkottu, M. Sharad, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan, "Cache Design With Domain Wall Memory", IEEE Transaction on Computers, 2014.
V. Rangha, V. Kumar, C. Augustine, A. Raghunathan and K. Roy, “Domain-Specific Many-core Computing using Spin-based Memory”, IEEE Transactions on Nanotechnology (TNANO), 2014.
2013
N. N. Mojumder, X. Fong, C. Augustine, S. K. Gupta, S. H. Choday, and K. Roy, “Spin-transfer torque MRAMs for low power applications,” ACM Journal on Emerging Technologies in Computing Systems (JETC), 2013.
G. Panagopoulos, C. Augustine, and K. Roy, "Physics-based SPICE-compatible Compact Model for Simulating Hybrid MTJ/CMOS Circuits", IEEE Transaction on Electron Devices (TED), 2013.
H. Naemi, C. Augustine, A. Raychowdhury, S. Lu, J. Tschanz, "STTRAM Scaling And Retention Failure", Intel Technology Journal, Vol. 17, 2013.
2012
C. Augustine, N. N. Mojumder, X. Fong, H. Choday, S. P. Park and K. Roy, “Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective”, IEEE Sensors Journal, 2012.
M. Sharad, C. Augustine, G. Panagopoulos and K. Roy, “Spin-Based Neuron Model with Domain Wall Magnets as Synapse”, IEEE Transaction in Nanotechnology (TNANO), 2012.
2011
C. Augustine, X. Fong, B. Behin-Aein, K. Roy, “Ultra-low Power Nano-magnet Based Computing: A System-Level Perspective,” IEEE Transactions on Nanotechnology (TNANO), 2011.
C. Augustine, A. Raychowdhury, D. Somsekhar, J. Tschanz, V. De and K. Roy, “Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances”, Transaction on Electron Devices (TED), 2011.
2010
N. N. Mojumder, C. Augustine, D. E. Nikonov and K. Roy, “Effect of quantum confinement on spin transport and magnetization dynamics in dual barrier spin transfer torque magnetic tunnel junctions,” Journal of Applied Physics, 2010.