Patents
2024
C. Augustine, A. Ghosh, M. Ostermayr, S. Subramaniam, P. Morrow, M. Khellah, and F. Merchant, "Device Technology Co-Design of single-port and multi-port SRAM with Complementary Transistors (CFET) and Intermediate Metal Layers", Filed with USPTO 2024.
C. Augustine, A. Ghosh, S. Subramaniam, P. Morrow, M. Khellah, and F. Merchant, "Balanced Static Random-Access Memory (SRAM)", Filed with USPTO 2024.
2023
R. Liu, S. Shahraini, T. Huusari, R. Dorrance, C. Augustine, B. Carlton, "Resonator aging Tracking", Filed with USPTO 2023.
C. Augustine, A. Ghosh, S. Subramaniam, P. Morrow, M. Khellah, and F. Merchant, "N-P Balanced Multi-Port Register File With Complementary Field-Effect Transistors (CFETs)", Filed with USPTO 2023.
2022
C. Augustine, S. Subramaniam, P. Morrow, and M. Khellah, "SRAM with P-type Access Transistors and Complementary Field Effect Transistor Technology", Filed with USPTO 2022.
C. Augustine, S. Subramaniam, P. Morrow, and M. Khellah, "Multi-port Register Files with CFETs", Filed with USPTO 2022.
C. Augustine, S. Subramaniam, P. Morrow, and M. Khellah, "Three-Transistor Embedded Dynamic Random Access Memory Gain Cell In Complementary Field Effect Transistor Process", Filed with USPTO 2022.
2021
C. Augustine, A. Afzal, K. Subramanian, A. Raman, P. Meinerzhagen, S. Bang, and M. Khellah, "Unified Retention And Wake-Up Clamp Apparatus And Method", Filed with USPTO 2021.
S. Bang, W. Lim, C. Augustine, E. Samson, M. Khellah, "Distributed And Scalable All-Digital Low Dropout Integrated Voltage Regulator", Filed with USPTO 2021.
2020
C. Augustine, S. Paul. K. Chen, M. Khellah, "Ultra-Deep Compute SRAM with High Compute Throughput and Multi-directional Data Propagation", Filed with USPTO 2020.
S. Bang, W. Lim, C. Augustine, E. Samson, M. Khellah, "All-digital voltage monitor (ADVM) with single-cycle latency", Filed with USPTO 2020.
W. Lim, M. Cho, T. Majumder, S. Paul, S. Bang, C. Augustine, M. Khellah, "Nearest neighbor search logic circuit with reduced latency and power consumption", Filed with USPTO 2020.
C. Augustine, S. Paul, T. Majumder, A. Koker, A. Lines, I. Rajwani, L. Striramassarma. M. Khellah, "Energy efficient memory array with optimized burst read and write data access, and scheme for reading and writing data from/to rearranged memory subarray where unused metadata is stored in a sparsity map", Filed with USPTO 2020.
Z. Chishti, S. Paul, C. Augustine, M. Khellah, "Nvram system memory with memory side cache that favors written to items and/or includes regions with customized temperature induced speed settings", Filed with USPTO 2020.
2018
C. Augustine. A. Choubal, A. Raman, F. Merchant, and M. Khellah, “Low Power Retention Flop with Support for Level-Sensitive Scan to Enable Low Power C1E state”, Filed with USPTO 2018.
C. Augustine, A. Afzal, K. Subramanian, A. Choubal, A. Raman, F. Merchant, and M. Khellah, “An all-digital stable closed loop retention clamp circuit for enabling new power state in core”, Filed with USPTO 2018.
S. Bang, M. Cho, P. Meinerzhagen, C. Augustine, M. Khellah, “Sleep Transistor with Optimally-Biased Gate-Voltage for Minimization of GIDL and Subthreshold Leakage Current in Sleep Mode”, Filed with USPTO 2018.
T. Majumder, S. Paul, C. Augustine, M. Khellah, “Computational CAM for spatiotemporal event representation”, Filed with USPTO 2018.
S. Paul, C. Augustine, T. Majumder, S. Bang, M. Khellah, "Multi-read and multi-write 6T SRAM with improved throughput for general matrix operations", Filed with USPTO 2018.
2017
C. Kuo, C. Augustine, B. Kung, "NDR-SRAM", Filed with USPTO 2017.
C. Kuo, C. Augustine, B. Kung, "N-NDR Latch", Filed with USPTO 2017.
B. Kung, C. Kuo, C. Augustine, B. Doyle, "Method to increase the negative differential resistance peak to valley ratio", Filed with USPTO 2017.
B. Pedroni, M. Khellah, O. Arad, B. Ravindran, S. Paul, C. Augustine, "Low power always on keyword spotting using sparse active spiking neural network", Filed with USPTO 2017.
S. Bang, W. Lim, M. Khellah, S. Paul, T. Majumder, C. Augustine, "Temporally processed acoustic feature for computation cost reduction of speech recognition", Filed with USPTO 2017.
2016
S. Paul. C. Augustine, M. Khellah, S. Sheik, "Energy Efficient Memory Organization for Spiking Neural Network with Sparse Connectivity", Filed with USPTO, 2016.
C. Augustine, S. Paul, S. Sheik, M. Khellah, "Spiking Neural Network with Stochastic Spike Transmission, Stochastic Membrane Potential and Stochastic Weight Update using Magnetic Tunneling Junction (MTJ)", Filed with USPTO, 2016.
C. Kuo, B. Kung, C. Augustine, "N-NDR latch", Filed with USPTO 2016.
C. Augustine, S. Kumar, C. Tokunaga, J. Tschanz, "3-D ReRAM Based PUF for IoT Applications", Filed with USPTO 2016
W. Wu, C. Augustine, S. Paul, "An efficient SRAM-based Spike History Table for Neuromorhpic Computing", Filed with USPTO 2016
S. Paul, C. Augustine, M. Khellah, " Forward Table-Based Presynaptic Event-Triggered Spike-Timing-Dependent Plasticity with Delayed Causal Updates", Filed with USPTO 2016
C. Augustine, R. Rios, S. Paul and M. Khellah, "Flip-Flop with Retention Feature Using Ultra Low-Leakage IGZO device for Embedded Applications", Filed with USPTO 2016.
S. Kumar, R. Kasim, C. Augustine, N. Lakamraju, B. Gill, "On-die die-level shorting margin structure using current sensor ", Filed with USPTO 2016.
2015
C. Augustine, W. Wu, S. Tomishima, S. Lu, J. Tschanz, "Circuit Architecture Co-Design to Improve Retention Failures in Dual MTJ STT-RAM", Filed with USPTO, 2015.
S. Tomishima, W. Wu, C. Augustine, S. Lu, "Twin Cell STT-RAM Read Method for Single Flip Error Detection", Filed with USPTO, 2015.
C. Augustine, S. Tomishima, J. Tschanz, S. Lu, "Bit Cell State Retention", Filed with USPTO, 2015.
C. Augustine, S. Tomishima, J. Tschanz, S. Lu, J. Tschanz, G. Panagopoulos, H. Naemi, "Magnetic Storage Cell Memory with Back-Hop Prevention", Filed with USPTO, 2015.
C. Augustine, S. Paul, "Low Power, Area Efficient and Non-volatile Learning Circuit for Spiking Neural Network using Magnetic Tunneling Junctions (MTJ)", Filed with USPTO, 2015.
W. Wu, C. Augustine, S. Tomishima, S. Lu and J. Tschanz, "Temperature Dependent Multiple Mode Error Correction", Filed with USPTO, 2015.
2014
H. Naeimi, S. Lu, C. Augustine, “Techniques to Improve STT Write Asymmetry”, Filed with USPTO, 2014.
C. Augustine, C. Tokunaga, and J. Tschanz, “Spin Torque Nano Oscillator (STNO) based Authentication Hardware”, Filed with USPTO, 2014.
H. Naeimi, S. Lu, C. Augustine, “Improving Spin Transfer Torque Write Operation with Merged RESET”, Filed with USPTO, 2014.
2013
C. Augustine, C. Tokunaga, and J. Tschanz, "Flip-Flop with Retention Feature Using Non-Volatile Spin-Transfer Torque Magnetic Tunneling Junction (STT-MTJ) for Embedded Applications", Filed with the USPTO, 2013.
"Retention flip-flop for power management providing 10ns save time, 700mV single-supply operation and 6 sigma restore", Filed with the USPTO, 2013.
C. Augustine, C. Tokunaga, and J. Tschanz, “Magnetic Tunneling Junction (MTJ) based Physical(ly) Unclonable Function (PUF) Circuits, Filed with the USPTO, 2013.
2012
A. Raychowdhury, C. Augustine, J. Tschanz, V. De, “A Digital Clamp for State Retention in Embedded Sequentials”, Filed with the USPTO, 2012