When you want something, all the universe conspires in helping you to achieve it (Paulo Coelho)


Charles Augustine,
Senior Research Scientist
Circuit Research Labs (CRL), Intel Corporation
Hillsboro, OR, USA
Adjunct Faculty, 
Washington State University,
Vancouver, WA, USA

My name is Charles Augustine and I am a Senior Research Scientist at Intel Circuit Research Labs

I am from Calicut (the name from which Calico is derived) in Kerala (called otherwise God's Own Country), India(the Land of Diversity). I have spend my entire childhood in Calicut. My primary school was LFUP School and later I moved to Jawahar Navodaya School for completing the high-school. Deeply motivated by the scientific and technological progress the World was going through and the prospects in which an engineer can contribute to accelerate the progress, I decided to pursue Engineering as my career and joined Birla Institute of Technology & Science, Pilani in Rajasthan, India and completed my Bachelors in Electronics.

After completing under-graduate degree, I worked in Bangalore (Silicon Valley of India), first at Texas Instruments Library Technology Development Group and later at Philips Semiconductors SoC Design Technology Group.

After a two years stint in the industry learning about engineering and business sides of technology, I decided to pursue PhD in United States. Five years later, in 2011, I received my PhD in the field of Silicon Nano-technology and Spintronics under the guidance of Prof. Kaushik Roy at Purdue University. In the same year I joined Intel Circuit Research Labs (CRL) to pursue a career in ultra low power circuit research in the industry. 

In Intel Circuit Research Labs, I am responsible for understanding and developing an ultra-low power state, which can enable faster entry and exit from sleep mode in high performance processors. With the help of optimized retention flop design and integration methodology with lower area and power-overhead, we can incorporate the ultra-low power state in designs where ultra-fast entry and exit from sleep mode is necessary and we have developed proof of concepts both in 14nm and in 22nm tri-gate CMOS process. Currently, I also serve as Adjust Faculty, in Washington State University, Vancouver