2016 San Diego

Andreas Olofsson (@adapteva) is currently the CEO at Adapteva, a fabless semiconductor companyhe founded in 2008. At Adapteva, Andreas' achievements include: creating the Epiphany manycore architecture,taping out 4 ASICs at 28nm and 65nm, reaching 50 GFLOPS/W in silicon in 2012, creating the Parallella project,winning the 2013 Facebook Open Compute Hackathon, and creating the open source parallel architecture library "PAL"and open hardware design library "OH!". Prior to Adapteva, Andreas was a senior designer at Analog Devices,where he led the datapath design team for the TigerSHARC DSP (#1 in energy efficiency) and invented the ISATG CCDsensor architecture that has shipped over 500M units to date. Andreas has a BS in Physics, BSEE and MSEE fromthe University of Pennsylvania (1996/1997).

Reinventing computing in the post-Moore era

After 50 years of unrelenting exponential Moore's Law progress, much of the high tech industry have built in

assumptions that the future will always bring cheaper, faster, better devices. The trillion dollar question today is:

what happens when the music stops? In this talk I will review "how we got here" and propose what will happen

to the semiconductor and software industry post-Moore. Insights are based on experiences from the crowd funded

many-core Parallella computing platform and Epiphany design work in leading edge processes.

Proceedings

Advances in Run-Time Performance and Interoperability for the Adapteva Epiphany Coprocessor

David Richie and James Ross

Implementing OpenSHMEM Model for the Adapteva Epiphany RISC Array Processor

James Ross and David Richie

Pattern Based Cache Coherency Architecture for Embedded Manycores

Jussara Marandola, Stephane Louise and Loïc Cudennec

Using Semantics-Aware Composition and Weaving for Multi-Variant Progressive Parallelization

Johannes Mey, Sven Karol, Uwe Aßmann, Immo Huismann, Joerg Stiller and Jochen Fröhlich

Evaluating Performance and Energy-Efficiency of a parallel Signal Correlation Algorithm on current Multi- and Many-Core Architectures

Arne Hendricks, Thomas Heller, Andreas Schaefer, Maximilian Kasparek and Dietmar Fey

Tabu Search for Partitioning Dynamic Dataflow Programs

Malgorzata Michalska, Nicolas Zufferey and Marco Mattavelli

Partition scheduler model for dynamic dataflow programs

Malgorzata Michalska, Endri Bezati, Simone Casale Brunet and Marco Mattavelli

A Fast Evaluation Approach of Data Consistency Protocols within a Compilation Toolchain

Loïc Cudennec, Safae Dahmani, Guy Gogniat, Cédric Maignan and Martha Johanna Sepulveda

Call for papers

(Also on WikiCFP)

Massively parallel processors have entered high performance computing

architectures, as well as embedded systems. In this

context, developers of parallel applications, including heavy

simulations and scientific calculations will undoubtedly have to cope

with many-core processors at the early design steps.

In the past sessions of the Alchemy workshop, held together with

the ICCS meeting, we have presented significant contributions on the

design of many-core processors, both in the hardware and the software

programming environment sides, as well as some industrial-grade

application case studies. In this 2016 session, we seek academic

and industrial works that contribute to the design and the

programmability of many-core processors.

Topics

Topics include, but are not limited to:

* Programming models and languages for many-cores

* Compilers for programming languages

* Runtime generation for parallel programming on manycores

* Architecture support for massive parallelism management

* Enhanced communications for CMP/manycores

* Shared memory, data consistency models and protocols

* New operating systems, or dedicated OS

* Security, crypto systems for manycores

* User feedback on existing manycore architectures

(experiments with Adapteva Epiphany, Intel Phi, Kalray MPPA, ST

STHorm, Tilera Gx, TSAR..etc)

* Many-core integration within HPC systems (micro-servers)

Submission

This yea