Architecture, Languages, Compilation and Hardware support for Emerging ManYcore systems


ALCHEMY Workshop 2016
Held in conjunction with the International Conference on Computational Science (ICCS 2016)
San Diego, California, USA, 6-8 June 2016

   The International Conference on Computational Science is an annual
    conference that brings together researchers and scientists from mathematics
    and computer science as basic computing disciplines, researchers from various
    application areas who are pioneering computational methods in sciences such
    as physics, chemistry, life sciences, and engineering, as well as in arts and
    humanitarian fields, to discuss problems and solutions in the area, to identify new
    issues, and to shape future directions for research.


Alchemy is scheduled on Wednesday 8th, 2016.
Room: Macaw
Complete program is available on the ICCS website.
Note to speakers: there is a 20-minute slot for each presentation (questions included), for both regular and short papers.


Andreas OLOFSSON, CEO and Founder at Adapteva Inc., USA

Andreas Olofsson (@adapteva) is currently the CEO at Adapteva, a fabless semiconductor company
he founded in 2008. At Adapteva, Andreas' achievements include: creating the Epiphany manycore architecture,
taping out 4 ASICs at 28nm and 65nm, reaching 50 GFLOPS/W in silicon in 2012, creating the Parallella project,
winning the 2013 Facebook Open Compute Hackathon, and creating the open source parallel architecture library "PAL"
and open hardware design library "OH!". Prior to Adapteva, Andreas was a senior designer at Analog Devices,
where he led the datapath design team for the TigerSHARC DSP (#1 in energy efficiency) and invented the ISATG CCD
sensor architecture that has shipped over 500M units to date. Andreas has a BS in Physics, BSEE and MSEE from
the University of Pennsylvania (1996/1997).

Reinventing computing in the post-Moore era

After 50 years of unrelenting exponential Moore's Law progress, much of the high tech industry have built in
assumptions that the future will always bring cheaper, faster, better devices. The trillion dollar question today is:
what happens when the music stops? In this talk I will review "how we got here" and propose what will happen
to the semiconductor and software industry post-Moore. Insights are based on experiences from the crowd funded
many-core Parallella computing platform and Epiphany design work in leading edge processes.


Advances in Run-Time Performance and Interoperability for the Adapteva Epiphany Coprocessor
David Richie and James Ross

Implementing OpenSHMEM Model for the Adapteva Epiphany RISC Array Processor
James Ross and David Richie

Pattern Based Cache Coherency Architecture for Embedded Manycores
Jussara Marandola, Stephane Louise and Loïc Cudennec

Using Semantics-Aware Composition and Weaving for Multi-Variant Progressive Parallelization
Johannes Mey, Sven Karol, Uwe Aßmann, Immo Huismann, Joerg Stiller and Jochen Fröhlich

Evaluating Performance and Energy-Efficiency of a parallel Signal Correlation Algorithm on current Multi- and Many-Core Architectures
Arne Hendricks, Thomas Heller, Andreas Schaefer, Maximilian Kasparek and Dietmar Fey

Tabu Search for Partitioning Dynamic Dataflow Programs
Malgorzata Michalska, Nicolas Zufferey and Marco Mattavelli

Partition scheduler model for dynamic dataflow programs
Malgorzata Michalska, Endri Bezati, Simone Casale Brunet and Marco Mattavelli

A Fast Evaluation Approach of Data Consistency Protocols within a Compilation Toolchain
Loïc Cudennec, Safae Dahmani, Guy Gogniat, Cédric Maignan and Martha Johanna Sepulveda

Call for papers

(Also on WikiCFP)

Massively parallel processors have entered high performance computing
    architectures, as well as embedded systems. In this
    context, developers of parallel applications, including heavy
    simulations and scientific calculations will undoubtedly have to cope
    with many-core processors at the early design steps.

   In the past sessions of the Alchemy workshop, held together with
    the ICCS meeting, we have presented significant contributions on the
    design of many-core processors, both in the hardware and the software
    programming environment sides, as well as some industrial-grade
    application case studies. In this 2016 session, we seek academic
    and industrial works that contribute to the design and the
    programmability of many-core processors.


    Topics include, but are not limited to:
    * Programming models and languages for many-cores
    * Compilers for programming languages
    * Runtime generation for parallel programming on manycores
    * Architecture support for massive parallelism management
    * Enhanced communications for CMP/manycores
    * Shared memory, data consistency models and protocols
    * New operating systems, or dedicated OS
    * Security, crypto systems for manycores
    * User feedback on existing manycore architectures
      (experiments with Adapteva Epiphany, Intel Phi, Kalray MPPA, ST
    STHorm, Tilera Gx, TSAR..etc)
    * Many-core integration within HPC systems (micro-servers)


 This yea
Procedia Computer Science
r, there will be two formats for the presentation at the
    workshop. The usual full-length paper is 10 pages according to the ICCS
    format, and the short-paper format well fitted for works in progress,
    with a maximum of 5 pages. The accepted papers for full-length paper
    will be published alongside with the ICCS proceedings in Procedia
    Computer Science
, whereas the short-papers will be presentation and
    poster only at the conference (with proceedings and presentations
    available from the workshop website).

 The manuscripts of up to 10 pages, written in English and formatted according to
    the EasyChair templates, should be submitted electronically.
    Templates are available for download in the Easychair right-hand-side menu
    in a “New submission” mode.

Program Chair

Aleksandar DRAGOJEVIC, Microsoft Research Cambridge, UK
Eric PETIT, Université de Versailles Saint Quentin-en-Yvelines, France
Antoniu POP, University of Manchester, UK

Program Committee

Jeronimo CASTRILLON, CFAED / TU Dresden, Germany
Camille COTI, Université de Paris-Nord, France
Tingxing DONG, Radeon Technologies Group, AMD, USA
Aleksandar DRAGOJEVIC, Microsoft Research Cambridge, UK
Daniel ETIEMBLE, Université de Paris-Sud, France
Vincent GRAMOLI, NICTA / University of Sydney, Australia
Sven KAROL, TU Dresden, Germany
Christos KARTSAKLIS, Oak Ridge National Laboratory, USA
Michihiro KOIBUCHI, National Institute of Informatics, Japan
Vianney LAPOTRE, Université de Bretagne-Sud, France
Stéphane LOUISE, CEA, LIST, France
Marco MATTAVELLI, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Maximilian ODENDAHL, Silexica / RWTH Aachen University, Germany
Eric PETIT, Université de Versailles Saint Quentin-en-Yvelines, France
Erwan PIRIOU, CEA, LIST, France
Antoniu POP, University of Manchester, UK
Jason RIEDY, Georgia Institute of Technology, USA
Thomas ROPARS, LIG / Université de Grenoble 1, France
Martha Johanna SEPULVEDA, Institute for Security in Information Technology, TU Munich, Germany
Philippe THIERRY, Intel Corporation, France

General Chair

SelectionFile type iconFile nameDescriptionSizeRevisionTimeUser