Call For Position Papers
The 1st International Workshop on Post-Moore's Era Supercomputing (PMES)
Co-located with SC16, Salt Lake City
Monday, 14 November 2016
Workshop URL: http://j.mp/pmes2016
CFP URL: http://j.mp/pmes2016cfp
Submission URL (EasyChair): http://j.mp/pmes2016submissions
Submission questions: pmes16@easychair.org
Workshop Description
This interdisciplinary workshop is organized to explore the scientific issues, challenges, and opportunities for supercomputing beyond the scaling limits of Moore's Law, with the ultimate goal of keeping supercomputing at the forefront of computing technologies beyond the physical and conceptual limits of current systems. Continuing progress of supercomputing beyond the scaling limits of Moore's Law is likely to require a comprehensive re-thinking of technologies, ranging from innovative materials and devices, circuits, system architectures, programming systems, system software, and applications.
The workshop is designed to foster interdisciplinary dialog across the necessary spectrum of stakeholders: applications,
algorithms, software, and hardware. Motivating workshop questions will include the following. "What technologies might prevail in the Post Moore's Era?" "How can applications effectively prepare for these changes through co-design?" "What architectural abstractions should be in place to represent the traditional concepts like hierarchical parallelism, multi-tier data locality, and new concepts like variable precision, approximate solutions, and resource tradeoff directives?" "What programming models might insulate applications from these changes?"
Experts from academia, government, and industry in the fields of computational science, mathematics, engineering, and computer science will have the opportunity to participate in the workshop as a presenter, panelist, or audience member. Invited speakers will provide insights and challenges from their disciplinary perspectives while peer-reviewed position papers on promising ideas will be presented to facilitate community interaction and diversity. Panel sessions will provide opportunities for interactions across disciplines and provocative questions from the audience.
Workshop Topics (not exclusive)
Technology trends and predictions
Alternative memory systems including non-volatile memory
Superconducting electronics
Alternative device technologies like CNT transistors
Quantum computing
Neuromorphic and brain-inspired computing
Probabilistic and stochastic computing
Approximate computing
2.5/3-D stacking approaches
Silicon photonics and optics
Computational science, data intensive, deep learning application drivers
Tools for or results from codesign of PMES systems
Performance studies of PMES systems
Modeling, simulation, emulation of PMES systems
Programming paradigms for PMES systems
Techniques for revolutionary improvements in energy efficient or power constrained supercomputing
Submission Invitation
The Organizing Committee invites the submission of position papers in the areas of interest for the PMES workshop. The Organizing Committee will review these position papers, and accept position papers for presentation at the workshop. Position papers should describe a research topic or question in next-generation hardware and software technologies, such as those topics listed above. This description should briefly address the following criteria:
Technology description: What technology (e.g., software, hardware, simulator) are you advocating, and what is its potential impact on architectures and/or applications?
SC challenges addressed: Which supercomputing challenges does this technology address?
Novelty: How is this approach different from existing solutions?
Maturity: How mature is this technology? Theoretical, lab demonstration, working prototype, fielded systems?
Risks: What are the hurdles to deploying this technology to the broad supercomputing community?
Authors of accepted position papers will be invited to participate in the workshop based on the overall quality of the position paper and our expectation that their inclusion in the workshop will stimulate constructive discussion by workshop participants. Unique or controversial positions that are well presented and emphasize transformative approaches to these questions will be given preference. Finally, all accepted position papers will be made available online on the workshop website.
Submission Format and Process
Submissions must conform to the following format:
2 pages in IEEE Transactions format
Abstracts (at the top of the template) are limited to 75 words.
Do not include
Keywords
Aurthor Bios
When using Latex, feel free to use our PMES template at pmes-latex.zip
Original IEEE word and Latex templates are available at http://www.computer.org/web/tpds/author
Cited references do not count against this page limit
The review process will be single-blind, in which the identities of the reviewers are not known to the authors
The paper may include any number of authors, but must provide contact information for a single "contact" author
There is no limit to the number of position papers that an individual or group can submit
Submissions must be received at the submission website http://j.mp/pmes2016submissions by the posted deadline.
Selected papers
Authors of position papers are invited to submit a journal length version of their work to IEEE Micro for our special issue. See the IEEE Micro CFP.
Important Dates
Submission site Opens: 17 April 2016
Submission Deadline: 17 June 2016 extended to July 1 AOE
Notification Deadline: 17 August 2016
Workshop: 14 November 2016
Organizing Committee
Co-chair: Prof. Satoshi Matsuoka (Tokyo Institute of Technology)
Co-chair: Dr. Jeffrey S. Vetter (Oak Ridge National Laboratory)
Prof. Keren Bergman (Columbia)
Prof. Tom Conte (Georgia Tech)
Dr. Erik Debenedictis (Sandia National Laboratory)
Prof. Franz Franchetti (Carnegie Mellon University)
Prof. Koji Inoue (Kyushu University)
Prof. Takeshi Iwashita (Hokkaido University)
Prof. Kengo Nakajima (University of Tokyo)
John Shalf (Lawrence Berkeley National Laboratory)
Prof. Richard Vuduc (Georgia Tech)
Prof. Gerhard Wellein (Erlangen)