INSTRUMENTATION II

2074 kartik bacc


1)) If the speed of input output device do not match the speed of the microprocessor, what types of data transfer techniques are used? Describe them with necessary block diagrams and control signals.

There can be 2 case considering the speed of microprocessor and peripherals. They are either microprocessor is faster or faster peripheral. Considering these 2 facts we can have following category of data transfer. They are :

  • Microprocessor controlled data transfer and
  • Peripheral controlled data transfer.

Microprocessor controlled data transfer is employed when microprocessor is faster otherwise peripheral controlled data transfer. We now talk about microprocessor controlled data transfer. This is of following types :

  • Unconditional data transfer
  • Data transfer using polling
  • Data transfer using interrupt
  • Data transfer using handshake signals
  • Data transfer using READY signal
  • Unconditional data transfers : In this data transfer microprocessor assumes that the peripheral is always available. Example seven segment display.
  • Data transfer using status check ( Polling ): In this data transfer microprocessor is kept in loop checking whether data is available.
  • Data transfer using interrupt signal: In this data transfer mechanism microprocessor keep continuing it's on routing task unlike status check type in which it is kept in a loop it has a clock cycle in which it checks for presence of interrupt if there is an interrupt than it stop the current cycle and go on continuing the interrupt request.
  • Data transfer with ready signal: Here the peripheral are very much slower than the microprocessor so one or more waiting T states are inserted into the clock cycle for data transfer completion.
  • Handshake signal :In this data transfer prior to data exchange some handshake signals are exchanged. This is of two types. They are :

Single handshake

Double handshake

Both of them can be achieved either using interrupt or status check. In single handshake the transmitter only inform the receiver that it is ready to transfer data but in case of double handshake the transmitter wait for an acknowledgement signal from the receiver whether it is ready to receive data.

Now we consider about Peripheral controlled data transfer what happens when peripheral is much faster than the microprocessor in this case we use peripheral controlled data transfer one of its widely used examples is

  • Direct Memory Access aka DMA in this data transfer mechanism microprocessor relinquishes the control over its bus and provide it to the peripheral which requests for DMA.

2 A microprocessor kit has an onboard 8255. Interface to the 8255 eight single pole double throw SPDT switches numbered S0 through S7 and a seven segment common anode LED display.Draw the complete circuit setup. Define clearly the functions of all ports. Write a program to initialize 8255 detect a switch closer , and display the value of the switch number on the LED display.

The complete setup for the circuit asked is drawn below:




Port Address Identification:

This figure is based on memory mapped I/O. So a 16 bit code is used as address bit.

Points to be noted :

· At first chip should be enabled i.e. A15 line should be low.

· For other ports:

A1 A0

PORT A 0 0

PORT B 0 1

PORT C 1 0

CONTROL REGISTER 1 1

  • All other bits A2 through A14 can be either at Logic 0 or at Logic 1 so the port address can be identified as follows:

PORTS PORT ADDRESSES IN HEX

A 8000H

B 8001H

C 8002H

Control Register 8003H

· Function of various ports:

Port A is used as input port

Port C is used as output port

Port B not used

To display character 0 through 7 on a seven segment display we need to look at the given below table:

PORT C PIN PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 HEX CODE

DIODE D8 D7 D5 D6 D4 D3 D2 D1

Switch Character

Pressed Displayed

NO LEDs

SWITCH OFF 0 1 1 1 1 1 1 1 7FH

S0 0 0 0 0 0 1 0 0 0 08H

S1 1 0 1 1 0 1 1 0 1 6DH

S2 2 0 0 0 1 0 1 0 0 14H

S3 3 0 0 1 0 0 1 0 0 24H

S4 4 0 1 1 0 0 0 0 1 61H

S5 5 0 0 1 0 0 0 1 0 22H

S6 6 0 0 0 0 0 0 1 0 02H

S7 7 0 1 1 0 0 1 0 0 64H

MULTIPLE 1 1 1 1 1 1 1 1 FFH

SPDTs

  • CONTROL WORD IDENTIFICATION :

D7 D6 D5 D4 D3 D2 D1 D0 CW HEX CODE

1 0 0 1 0 0 0 0 90H

Program Source Code :

MVI A, 90H

MVI B, 02H

MVI C, 09H

STA 8003H ;(Ports are Initialised)

LDA 8000H

ROTATE: DCR C

JZ START

RAL

JC COUNT

JNC ROTATE

COUNT: DCR B

JZ MSS (Multiple SPDTs Switched)

JNZ ROTATE

START: LDA 8000H

ADD FFH

JNC OFF (No switch closed)

LDA 8000H

ADD FEH

JNC ZERO (S0 closed)

LDA 8000H

ADD FDH

JNC ONE (S1 closed)

LDA 8000H

ADD FBH

JNC TWO (S2 closed)

LDA 8000H

ADD F7H

JNC THREE (S3 closed)

LDA 8000H

ADD EFH

JNC FOUR

LDA 8000H

ADD DFH

JNC FIVE

LDA 8000H

ADD BFH

JNC SIX

MVI A 64H (Displays 7)

STA 8002H

JMP START

OFF: MVI A 7FH (All LEDs OFF)

STA 8002H

JMP START

ZERO: MVI A 08H (Displays 0)

STA 8002H

JMP START

ONE: MVI A 6DH (Displays 1)

STA 8002H

JMP START

TWO: MVI A 14H

STA 8002H

JMP START

THREE: MVI A 24H

STA 8002H

JMP START

FOUR: MVI A 61H

STA 8002H

JMP START

FIVE: MVI A 22H

STA 8002H

JMP START

SIX: MVI A 02H

STA 8002H

JMP START

MSS: MVI A FFH (Multiple SPDTs Switched & Turn On D8)

STA 8002H

JMP START

3.(a) Explain the design of a USB to rs232 adapter with neat circuit diagram, appropriate voltage translation chips and necessary handshake control signal.

Ans The following circuits explain the connection:

Main chips involved are:

(a) FT 232R – USB to serial UART interface

(b) MAX 232 – RS232 Level Shifter

3.b What is the time required for transmission of a character with one start bit,7 data bits ,one parity bit and one stop bit with 1,200 baud?

Total bits in the character = 1 + 7 + 1 + 1 =10 bits.

Time required to transfer 10 bits =1/1200 seconds.

Time required to transfer 10 bits =1/1200 ×10=8.33 millisecond.

4. The data converter that is being used in your project is suffering from differential nonlinearity and harmonic distortion.Instead of purchasing a new converter you are required to use defective converter.Discuss technical measures that can be implemented to mitigate the aforementioned errors.

Ans Those frequencies which are out of bandwidth interest contributes to harmonic distortion to prevent this anti-alias filters should be used and its maximum frequency should be half the sampling rate of sample and hold circuit and this is based upon Nyquist criteria. This anti-alias filter cuts-off all other higher frequencies beyond bandwidth of interest and prevent harmonic distortion.The following below diagram explains this:

Differential non-linearity is used to measure the difference between analogue values of two adjacent digital input. Differential non linearity is represented by following given formula:

DNL[i]=(M.V.[i]_M.V.[i-1])

M.V.=Measured Value

To mitigate the effect of differential nonlinearity follow as follows:

1. Conduct digital to analogue operation with DAC and record the data.

2.Find out corresponding differencial voltage for each digital input as follows:

Differencial Voltage,d[i] = Videal[i] - Vmeasured[i]

3. Calculate the compensation current for that differential voltage d.

Compensation Current,I[i]=d[i]/Rf[i]

4. Calculate the value of corresponding resistance to obtain this current as follows:

R[i]=I[i]/5

5. Positive supply for those binary codes whose measured value is greater than ideal value and negative supply for reverse.

5.b. Signals from 3 transducers are to be recorded in data logger.The analogue signal supplied by the three transducers are dual polarity (-50 mv to +50 mv) having frequency is 5 KHz 10 KHz and 15 KHz. Explain the design of the following steps of the data logger.

  1. Input scanner off the data logger such that it can appropriately sample the incoming signals [3]
  2. Signal conditioner of stages if the 8 bit ADC used inside the data logger accepts only positive polity signals ranging from 0 volt to 5 volts.

ANS

Figure drawn above assists the explanations.

Explanation of the design of input scanner:

The highest frequency amongst the input signal is 15 KHz. Using Nyquist criteria the sampling rate should be 30KHz. The programmer periodically scans all these three inputs for a particular time and the scan signal are fed to the next stage.


Explanation of the design of signal conditioner:

As given in question transducers polarity varies from - 50mV to 50mV but the ADC can only accept positive polarity signals so this transducer signals must be biased at appropriate DC level. We maintain this level at 2.5V using and OP-amp virtual ground concept. This raises the reference ground at 2.5 volts virtual ground and assists proper analogue to digital conversion. An IC named TLE2425 can be used to generate 2.5 DC volt by providing it 5 volt dc.


6. Explain the mechanism of filtering line noise with the aid of chokes. How does a choke differentiate between the signal that it needs to pass and the noise that it needs to suppress? Describe the circumstances where chokes are preferred over other noise filtering approaches?

Ans>> Chokes in actual is an inductance and XL=2ῳL so it offers high impedance to high frequency and low impedance to low frequency in this manner the high frequency components are rejected and low frequency component low frequency components finds it easier to pass high frequency components are suppressed and the signal is flattened.

Chokes differentiate noise and signal on the basis of frequency.The circumstance where chokes are preferred over other noise filtering process are as follows :

· To surpass high frequency component from the signal.

7. During circuit design process what are some general technical dilemmas faced by engineers explain how an engineer can arrive at an optimal solution given the requirements of a customer?

Ans>> Technical dilemma faced by engineer are as follows :

                  • Selection of Technology
                  • Reliability,
                  • Fault tolerance,
                  • High speed design,
                  • Low power,
                  • Noise & error budget

Experience is the best solution to arrive at optimal solution but this is not always the case. We have to strive with the issues given above and for every particularly issue we have different circumstances the way we should tackle with the problem. At first must have an clear idea about the region of frequency we are going to work with. This helps us in selection of technology that will be used in particular frequency range. like whether we are going to use micro-strip lines ,waveguide , Radio frequency design, PCB, discrete components etc. After that we have to choose technology that how we are going to do the design and this may refers to solutions like microprocessor based design, microprocessor controlled design, standard cells, gate arrays ,custom design. Even knowing all this fact we have to consider on a lot of facts about technology we are going choose like if even if we choose microprocessor we have to must have idea about its performance, cost, power dissipation, speed, different peripherals it have and memory etc.

8.(a). In a multilayer PCB, describe how grounding is performed and how coupling amongs the layers is minimized?

In a multilayer PCB a separate plane is assigned as ground plane and this plane is kept as close as possible to power plane. These two layers are separated by a thin layer of dielectric material.

Proper grounding and shielding concern help counter the effects of coupling.

Following points help minimise coupling amongst the layer in a multilayer PCB:

                • Keep as minimum as possible separation between return and ground planes
                • Don't create any break in either power plane or return plan. This breaks increase effective inductance and hence effective impedance.
                • Use copper foil between analogue traces and ground the foi.l
                • Increase separation between signal traces.This will help decrease capacitance between lines.

C=Ɛ A/d

d= Sepration between signal traces

                • Place decoupling capacitor near IC packages.
                • Don't run parallel traces for long distance.
                • Isolate Chip Select, Chip Enable, Read,Write lines.These increase cross talk in other lines.

8.(b). A faulty computer motherboard has severe clock jitter. The Crystal producing the clock pulses is functioning properly but clock signals arriving at various motherboard chip suffer from jitter discuss the source of the problem and provide some remedies.

The sources of problems are as follows:

1. Crosstalk

2. Ground bounce

3. Propagation delay

》》 The remedies are as follows:

1. Avoid long parallel running signal lines .

2. Use decoupling capacitor.

3. Use the technology which has same rising time and falling time.

9.(a) Discuss the shortcomings of existing software development models, and suggest measures to overcome them.

There are three software development models. They are as follows:

1. Waterfall model

2. Prototyping model

3. Spiral model

Their shortcomings along with measures to overcome them are explained below.

Shortcomings of waterfall models are as follows:

            • It assumes sequential evolution of software development which in real life is seldom true.
            • Software available only late in the development schedule.
            • In it the most of bad point is that requirement evolves due to application changes or expands or customer does not know all of them at beginning.

Measures to overcome the shortcomings are as follows:

            • Eliminate sequential evolution of software use iterative process and the iteration should be such that it can iterate from any successor steps to any predecessor step.

The shortcomings of prototyping model are as follows:

            • Its biggest problem is that thorough testing and documentation are easily forgotten and
            • Creeping featurism

Some points that lead to overcome the shortcomings of prototype are as follows:

            • Use prudent decision on the step evaluation by customer and
            • Keep the number of iteration within a certain limit.

The limitation of spiral model is that it is very much complex and time consuming and the way it can be overcome is use less number of iteration to get the software into the market in short time.

9.b)) The testing time for software cannot be too long,yet software needs to be to be thoroughly tested before it can be commercialised. Explain how this paradox is overcome in a real-world software development environment?

After coding completion software developed should be thoroughly tested. These testing can be :

                    • Black box testing or
                    • White box testing.

Black box testing consider only input and output interface. This testing has no concerns with how software works. This is noway a through testing but, most frequently adopted in real world environment for quick testing.

But for a more intimate testing such testing all logical decisions and functional modules within a software may require lots of year for entire combination testing. That is a chore cumbersome task. This lengthen the time to market and hence leads to costlier product. For white box testing the best way is to use real world software development environment which generates a predefined stimulation and record the responses.Help trace down the bugs and shorten and the testing mechanism.

This is how the real world software development environment overcome the paradox :-

“The testing time for software cannot be too long,yet it needs to be thoroughly tested before it can be commercialized.”