SOLUTIONS-TO-QUESTIONS - 2072 CHAITRA REGULAR

INSTRUMENTATION II

2072 CHAITRA REGULAR

4.B Interface a suitable DAC using 8255 PPI to a 8085 microprocessors to generate a square wave oscillator between 0V and -5V having a frequency of 1 KHz. Show the interfacing circuit and the necessary program.[3+3]

Ans The necessary interfacing circuit is drawn below using a 8255 PPI and a 1408 DAC. The cicuit outputs 0V for 10000000=10H while -5v for 00000000=00H DAC output.

The program is as follows:

PORT A ADDRESS 0000H

CONTROL REGISTER ADDRESS 0003H

CONTROL WORD 10010000=90H

ASSUMPTION 8085 CLOCK FREQUENCY OF 1 MHz

8085 CODE:

MVI B,46H ; counter initialization(46h=70)

MVI A, 90H

STA 0003H

MVI A,OOH

STA 0000H

CALL DELAY

MVI A,10H

STA,0000H

CALL DELAY

HLT

DELAY : DCR B ; a 1ms time delay subroutine

JNZ DELAY

RET

6.a Explain the remedial strategies for various energy coupling mechanisms?

There are four types of energy coupling mechanism. They are :

Conductive energy coupling mechanism
Inductive energy coupling mechanism
Capacitive energy coupling mechanism and
Electromagnetic energy coupling mechanism.

These energy coupling mechanisms couple unwanted energy to other circuits. So remedies measure must be adopted to reduce their effects. These remedial strategies are discussed below:

For conductive energy coupling mechanism:

Filtering is the only mechanism to prevent conductive energy coupling. Filtering can be done on following basis:

Frequency
Amplitude
Mode

For inductive coupling mechanism:

Minimise loop area
Use decoupling capacitor
Use of ferrite beads
Shield the circuit with high permeable enclosures like Mu-metal shield and steel enclosures.
Minimise bandwidth of the signal so that the bandwidth of interest only goes under operation
Use of twisted pair cable

For capacitive coupling mechanism

Braided Shield and metal enclosures
Increase separation between signal Treasures
Use pulses with slow transition

For electromagnetic energy coupling mechanism

Shielded enclosures
Good layout and signal routing
Reduced bandwidth
Length of transmission line should be greater than 1/20 of signal wavelength i.e.tp >tr/4

6.(b) An electronic circuit receives noise from switching element. If voltage on the switching device swings from 4 volt to 6 volt within 100 microsecond, during which current makes a transition from 10 microampere to 25 microampere in 10 nanoseconds, what might be the noise coupling mechanism? Identify it using suitable calculations.

Ans: Pseudo impedance=dv/dt/di/dt

dv/dt=(6-4)/100*10-6

di/dt=(25-10)*10-3/10*10-9

Pseudo impedance=13.33<<377

Hence,inductive coupling.

7. DOECE is looking for an expert engineer to walk in the search project of high frequency highest paid applications what guidelines would you suggest as an engineer to design higher speed and high frequency circuit explain in details.

The guidelines I would suggest as an engineer to design high speed and high frequency circuit are explained below;

Length of signal path should be greater than 1/20 of maximum wavelength of the signal.i.e. L>⋌/20
Rise time of the signal should be less than 4 times the propagation delay of the signal path.i.e.Tr<4Tp
Use a decoupling capacitor near each chip for two sided boards.
Use of ferrite bead at the power entry points
Increase the Rise and fall times of the signal edges.
Impedance Matching
Placing the high frequency high speed component near the connector.
Calculate the maximum interconnection for a particular logic family on the basis of their rise time
Taking remedial measures for ground bounce such as:
- Reducing loop inductance
- Reducing the input get capacitance and
- Choosing logic families that either control the signal transition or have slow fall times.

Taking remedial measures for crosstalk like:

decreasing the coupling length and the characteristic impedance and
increasing rise time of the signal will reduce crosstalk

8. Circuit boards combined electronic components and connectors into a functional system through electrical connections and mechanical support.Explain the factors that need to be considered while creating traces to connect the electronic components.

The factors that need to be considered while creating traces are below:

Trace density: number of traces per unit area. Denser traces allow denser component placement while sparser traces allow sparser components placement. Sparser traces will help reduce cost of materials but it also cost to producing fine lines and may degrade signal integrity.
Common impedance: Minimise the number of circuits that share the same return path. It would be better using return or ground plane.
Distribute signal and returned carefully: In single sided PCB signal and return line should be placed such that they make as small as possible loop. The length of signal and return traces should be of same length
Transmission line concern: Consider the factors like:
- rise time and fall time of the signal,
- propagation time and characteristic impedance of the transmission line.
- shortening interconnection length,
- use material having low dielectric constant which help in a speeding the signal velocity

5. Trace impedance and matching: The terminating resistance R0 should match the characteristic impedance Z0 of the transmission line such that no reflection occurs at the endpoints otherwise this may degrade the performance of the circuit like false switching.

6. Avoid cross talk:

Increase separation between conductors
Shield clock lines with guard strips
Reduce magnetic coupling by reducing the loop area of circuits
Sandwich signal line between return plan to reduce crosstalk
Isolate the clock, chip select, chip enable, read and write lines
Don't run parallel traces for long distance particularly asynchronous signals.

9. A software company is planning to make few software.Suggest good processor to develop software. Explain different types of software models.

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