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To the left is the phase locked loop encased in a copper low noise enclosure used for FM Demodulation.
Figure 1 above.) Phase Locked Loop System in low noise enclosure
Figure 2 Left.)This is the block diagram for the phase locked loop system. It gives the locations of the capacitors and resistors that are used to control the center frequency, frequency range, and lock range for the system.
Figure 4 is taken from the spec sheet for the 4046 Phase Locked Loop chip. This figure is especially useful because it allows the user to calculate the resting phase difference between the actual signal and the square wave produced by the chip that is locked onto the incoming signal. The mixer gain can be determined by the slope of figure 4 between 90 and 180 degrees (since this is where we are operating at) and is calculated to be about 1.59 Volts.
The graphs depicted to the left are taken from the spec sheet for the 4046 phase locked loop chip and are used to size various components. The capacitor C1 and resistor R1 control the center operating frequency for the phase locked loop and can be sized using the first graph at the top. The Resistor R2, when coupled with C1, will control the frequency offset, or acquiring range, for the phase locked loop and can be sized by using the middle graph. The last graph is for determining the locked range, which is the range the phase locked loop chip can be locked on to the input signal, and is sized by the ratio between R2 to R1.
Figure 5 above.) Plots for sizing capacitor capacitor (C1) and resistors (R1 and R2)
The 4046 phase locked loop chip follows the feedback block diagram depicted on the left.
Figure 6 above.) Phase Locked Loop Block Diagram
To the left is the simplified feedback loop of the phase locked loop chip. This is the simplified transfer function for the phase locked loop in an appropriate form capable of being input to Matlab for simulating the step and impulse responses. It should be noted that in reality this transfer function is multiplied by the constant 2pi/RC, which only effects the amplitude not the shape of the resulting step response.
Figure 7 above.) Simplified Transfer function block diagram for phase locked loop
In order to model the step response of the phase locked loop system, The mixer gain and sensitivity for the system must be measured. The following graphs were taken using different values of capacitance C1 (50pf, 500pf, 4700pf), in order to accurately model the system.
In order to model the step response of the phase locked loop system, The mixer gain and sensitivity for the system must be measured. The following graphs were taken using different values of capacitance C1 (50pf, 500pf, 4700pf), in order to accurately model the system.
For the 50 pF capacitor, the following data for voltage out of the voltage controlled oscillator vs frequency was recorded. The inverse of the average slope of this line would be the sensitivity since it has units of hertz per Volt, and for this capacitor came out to about 66.6 Khz / V
Figure 8 above.) Change in Voltage for a frequency sweep of the 50pf capacitor
For the 500 pF capacitor, the following data for voltage out of the voltage controlled oscillator vs frequency was recorded. The sensitivity for this capacitor is 12.5 Khz / V.
Figure 9 above.) Change in Voltage for a frequency sweep of the 500pf capacitor
For the 4700 pF capacitor, the following data for voltage out of the voltage controlled oscillator vs frequency was recorded. The sensitivity for this capacitor is 1.5 Khz / V.
Figure 10 above.) Change in Voltage for a frequency sweep of the 4700pf capacitor
Phase Locked Loop used for FM Demodulation:
Phase Locked Loop used for FM Demodulation:
By modulating the frequency input to the phase locked loop, simulating an FM signal, the phase locked loop's response can be both observed on an oscilloscope and modeled in MatLab. The first set of images are taken from the 500pf capacitor, whereas the second set of images are taken from the 4700pf capacitor. The last set of images displays the MatLab code used to produce the graphics for the step responses from the simplified transfer function of the pll system. The left most image depicts the code for the 500pf capacitor and the rightmost image depicts the code used to generate the 4700pf capacitor step response.
Figure 11 Left.) Phase Locked Loop response using 500pf cap
Figure 12 Right.) Matlab response for 500pf cap
Figure 13 Left.) Phase Locked Loop response using 4700pf cap
Figure 14 Right.) Matlab response for 4700pf cap
Figure 15 Left.) MatLab code used to generate figure 12.
Figure 16 Right.) MatLab code used to generate figure 14.
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