Overview

Introduction to SystemVerilog: language features to support both design and verification. Good practices for simulation and synthesis, techniques for constructing reusable testbenches. Additional topics may include hardware acceleration and transaction-based verification techniques.

Course structure:

• Lectures

• Homework

• Exams

• Project

A formal course description can be found here:

https://www.pdx.edu/electrical-computer-engineering/ece-571-introduction-system-verilog-design-and-verification

Required TA Skills

1. Be proficient in SystemVerilog and C or C++

2. Must have solid digital design skills (data paths, controllers)

3. Possess good written and verbal communication skills, and behave at all times with integrity and fairness

TA Responsibilities

1. Grade homework and quizzes in a timely manner and upload student scores and feedback to D2L.

2. Monitor D2L discussion threads and comment/reply where appropriate, alerting the instructor when necessary.

3. Hold office hours for 2-4 hours per week; be responsive to student email questions, assist students as required/directed with S/W tools (e.g. Mentor Questa, cross-compilers, simulators, frameworks).

4. There may be other responsibilities depending on the instructor such as holding exam review sessions, proctoring or grading exams, or other assistance to the instructor if requested.

5. Be in contact with the instructor and keep them informed of any problems observed in homework or office hours.

Verifying Your Qualifications

• TA candidate must have completed ECE 571 with an A grade.