Results

Thank you to all the finalists, judges, and student leads who came to CSAW 2019!

After considering the level of attack success and the quality of the students' presentations, posters and engagement with the judges, the judges awarded:

1st Place: CMU | 2nd Place: NuLogiCS | 3rd Place: IO

Combinational Circuit Challenges --- Details

Two sets of circuits were provided to contestants, one set with oracles, and one set without. Each set contained:

small circuit: #Inputs: 522 #Outputs: 512 #Key: 80 (40 RLL + 40 SFLL-fault)
medium circuit: #Inputs: 767 #Outputs: 757 #Key: 120 (60 RLL + 60 SFLL-fault)
large circuit: #Inputs: 1452 #Outputs: 1445 #Key: 160 (80 RLL + 80 SFLL-fault)

We also provided a single bonus circuit with oracle: #Inputs: 892 #Outputs: 1746 #Key: 256 (128 RLL + 128 SFLL-fault)

This table shows the current number of key bits recovered by the teams that are verified as correct.

Where the result is stated as ( - ) the team did not provide any results.
Where the result is stated as (x / y), the team report y bits recovered, of which only x are verified as correct.

Sequential Circuit Challenges --- Details

Two sets of circuits were provided to contestants, one set with oracles, and one set without. The set featured:

small circuit 1: #Inputs : 13, #Outputs : 87, Length of Key sequence : 52
small circuit 2: #Inputs : 41, #Outputs : 35, Length of Key sequence : 63
medium circuit 1: #Inputs : 11, #Outputs : 121, Length of Key sequence : 103
medium circuit 2: #Inputs : 18, #Outputs : 14, Length of Key sequence : 51
large circuit 1: #Inputs : 36, #Outputs : 32, Length of Key sequence : 134
large circuit 2: #Inputs : 21, #Outputs : 13, Length of Key sequence : 162

Width of key in each clock cycle : 3-bits to 5 bits (not a fixed width for all clock cycles)

Key input ports used in each clock cycle: Different (not a fixed set of ports for all clock cycles)

In this table:

"-" --> nothing has been reported
"y/x" --> y = reported, x = actual

None of the teams could report the correct sequence and associated key input ports. However, they could report a subset of key input ports that are being used for key assertion.

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