Alric Althoff is a Senior Research Scientist at Leidos. His research activities span hardware security, hardware/software co-design, computer vision, and machine learning. His recent work is on metrics and protocols for assessing hardware assurance, and machine learning-driven co-design. All his work, in some way or other, seeks to challenge the traditional assumptions baked into accepted practice. He obtained the BS degrees in Computational Mathematics and Cognitive Science, and the MS and PhD in Computer Science, from UC San Diego.

Cayley Rice is a Senior Mathematician, Solution Architect, and SoC project lead at Leidos. Her current R&D efforts are in building trustworthy SoCs to support compute-intensive signal processing. She is a multifaceted learner and educator with expertise in signal processing algorithms, RF and IR sensors, scenario simulation, and mathematics instruction. She has led several Leidos processor efforts, including requirements definition, design, verification, and test. She earned the BA degree in Mathematics from Swarthmore College, and the MA and PhD in Mathematics from UC San Diego.

Joe Tostenrude has been with The Boeing Company for 20 years and serves as a Program Manager for the Solid State Electronics Development group within Boeing Research & Technology. Joe manages System-on-Chip (SoC) design and design methodology programs in the areas of Trusted and Assured Microelectronics, Radiation Hardening By Design (RHBD), extreme environments, and autonomy. Joe holds a BS in Electrical Engineering from the University of Portland and an MS in Electrical Engineering from the University of Washington.

Matthew French is a Research Director in the Computational Systems and Technology group at University of Southern California’s Information Sciences Institute applied research lab where he facilitates large scale, cross-discipline research which spans the institute. In this capacity, Mr. French serves as the director of the SecUre and Robust Electronics (SURE) center at ISI, which conducts research and provides services in hardware trust, security, reliability, and resiliency. Mr. French also oversees the Reconfigurable Computing Group at ISI, which performs research in application mapping, hardware / software co-design, CAD tools, and front-end ASIC design. Mr. French has served at ISI for over 20 years, primarily as PI on over $40M of research projects, spanning multiple agencies (DARPA, IARPA, NASA, AF, and others) and scope (system, sub-system, and device level). Prior to ISI, Mr. French was in the SIGINT directorate at Lockheed Sanders, where he worked on deployed systems.

Peter Gadfort received a B.S. in electrical and computer engineering in 2008, a M.S. in electrical engineering in 2009, and a Ph.D. in electrical engineering from North Carolina State University in 2014. He was an intern/postdoctoral researcher at University of Southern California’s Information Sciences Institute (ISI) in 2013-2014 before joining CCDC-ARL in the fall of 2014. His current research interests include 2.5 and 3-D packaging and integration, secure microsystems, and energy efficient electronics.

Dr. Michael Vai joined MIT Lincoln Laboratory in 1999 and is currently Senior Staff in the Secure Resilient Systems and Technology Group. Before coming to this group, he was Assistant Leader of the Embedded and Open Systems Group in the ISR and Tactical Systems Division. At Lincoln Laboratory, he has led the development of several notable real-time systems incorporating very-large-scale integration (VLSI) chips, field-programmable gate arrays (FPGAs), and multicore processors.

Dr. Vai has worked in the area of high-performance embedded computing for more than 20 years. He has worked and published extensively in VLSI, application specific integrated circuits (ASIC), FPGAs, design methodology, and embedded digital systems. He has published more than 100 technical papers and a textbook (VLSI Design, CRC Press, 2001). He is also the co-editor and a contributing author of a reference handbook (High Performance Embedded Computing Handbook, CRC Press, 2008).

Until July 1999, Dr. Vai was on the faculty of the Electrical and Computer Engineering Department, Northeastern University, Boston, Massachusetts. Dr. Vai's current research interests include secure embedded systems, and particularly those applicable to critical missions. He is a senior member of IEEE. Dr. Vai received his MS and PhD degrees from Michigan State University, East Lansing, Michigan, in 1985 and 1987, respectively, all in electrical engineering.

Nicole Fern is a senior hardware security engineer at Tortuga Logic whose primary role is providing security expertise and defining future features and applications for the product line. Before joining Tortuga Logic in 2018 she was a postdoc at UC Santa Barbara. Her research focused on the topics of hardware verification and security. She received her undergraduate degree in Electrical Engineering from The Cooper Union for the Advancement of Science and Art in 2011 and her Ph.D. from the Electrical and Computer Engineering department at UC Santa Barbara in 2016.

Peilin Song is a Research Staff Member at the IBM Thomas J. Watson Research Center, where he is a manager of the Circuit Diagnostics and Testing Technology department. He joined IBM in 1997 and has since worked in the area of design for testability, fault diagnostics, fault modeling, circuit simulation, optical testing and diagnostics, and recently hardware security. He has 80+ publications, holds 37 U.S. patents with several patents pending. In 2004, he has won the IEEE Electron Device Society Paul Rapparport Award. Also, in 2006, he received an Outstanding Contribution Award from the IEEE Computer Society. He received his Ph.D. in electrical engineering from the University of Rhode Island.

Andrew Howard currently works at NAVAL SEA SYSTEMS COMMAND (NAVSEA), Global Deterrence & Defense Department in Crane Indiana. He has spent his career supporting strategic system programs (SSP) of the Navy with a specialty in digital test and reliability. Andrew has been focused in counterfeit and trust while currently serving as the Navy functional verification and validation (V&V) Lead for the Joint Federated Assurance Center (JFAC). In his new role as digital technologist he focuses on parts issues and recommendations for major programs.

Andrew is a graduate of the Electrical and Computer Engineering departments of Purdue University and MBA/MS finance from Indiana University.