Research

Research Groups

ACE Group (ArChitecturE and Platform): This group focuses on the design and optimization of parallel computing systems and architectures. 

• Current Topics: 

  • Data Processing Architectures

  • In/Near Memory Processing

  • FPGA Implementation

  • Applications: Machine Learning, BigData Analytics, Genomics, Bioinformatics, Bio-Signal Processing

PAL Group (PAralleL Application and Design): This group emphasizes on the design of parallel applications.

• Current Topics: 

  • Machine Learning

  • BigData Analytics

  • Genomic Analytics

  • Bio-signal Processing

MET Group (METhodology and Flow): This group works on the design methodology and optimization flow of a parallel system. 

• Current Topics:

  • Heterogeneous and Emerging Data Processing 

  • Model of Parallel Systems and Applications

  • System Compiler 

  • Optimization Flow and Algorithm

Funded Projects

System Compilation and Architecture Tuning of Exa-scale Deep Learning Models for Reconfigurable Processing Array on Near Memory Computing Platform (2022.8~2025.7) (MOST 111-2221-E-A49-092-MY3) (PI)

Software/Hardware Co- Design Framework for a Reliable and Low Latency Machine Learning System (2022.10~2024.9) (NSTC 111-2623-E-A49-007) 

Deep Learning Model Optimization and Software Hardware Co-design Flow (2021.12~2023.3) (PI)

Performance Analysis of In-Storage Computing for Database Management System (2021.12~2023.3) (PI)

SW/HW Acceleration Techniques for Intelligent Processing on Distributed Relational Database, (2019.8~2022.7) (MOST 108-2628-E-009 -007 -MY3)  (優秀年輕學者研究計畫) (PI) 

Distributed Genome Assembly Acceleration Technique for Near DRAM Computing, (2020.11~2022.4) (科技部產學計畫) (PI)

EDA solutions for memory-centric AI edge: system evaluation and implementation for reconfigurability, (2019.11~2021.10) (Co-PI)

Collaborative Artificial Neural Network Computing Platform using In-Memory-Processing Technique, (2018.1~2021.12) (Co-PI)

Sensing, Analyzing, and Computing Technologies for Industrial Big Data based on Field Studies, (2017.5~2020.4) (Co-PI)

近DRAM資料處理（Near DRAM Processing）系統運算架構與效能評估, (2019.4~2020.3) (PI)

Hardware/Software Solutions for Shared Memory Management of Heterogeneous Many-core Computing Platforms, (2016.8~2019.7) (MOST 105-2628-E-009 -004 -MY3) (優秀年輕學者研究計畫) (PI)

前瞻技術產學合作計畫－前瞻下世代行動通訊終端關鍵技術研究, (2015.10~2017.9) (MOST 104-2622-8-002-002, MOST 105-2622-8-002-002) (Co-PI)

Design and Optimization of High-Performance Density Estimation Algorithm for Big Data on a Heterogeneous Many-core Platform, (2015.8~2016.7) (MOST 104-2221-E-009-079) (PI)

前瞻技術產學合作計畫－SDN-enabled Cloud-based Wireless/Broadband Network Technologies & Services-D1: Chip Design and System Architecture for SDN Switches, (2014.8~2016.7)

教育部智慧電子整合性人才培育計畫－高階應用處理器(AP)聯盟-模組課程發展計畫, (2015.3~2016.2) (PI)

新型術中脊髓神經電生理監測系統之研發－總計畫暨子計畫－脊髓神經電生理訊號及監測系統之分析與評估, (2013.8~2016.4) (MOST 102-2220-E-002 -028) (Co-PI)

交通大學-京元電子 鑽石計畫實驗室－CIS Tester Structures 研究開發計劃, (2012.8~2015.12) (Co-PI)

教育部-智慧電子整合性人才培育計畫－多核心系統硬軟體設計課程發展計畫, (2012.11~2014.2) (PI)

教育部-高階應用處理器(AP)聯盟中心-主題領域系列課程開授計畫－異質多核系統硬軟體設計子領域, (2012.12~2014.2) (PI)

教育部-智慧電子前瞻技術系統(SLD)設計課程發展計畫－多核架構發展暨其應用, (2011.10~2013.2) (PI)

Hardware Design of Adaptive Network and Virtualization Coprocessor for Green Cloudlet Serve On Chip (2011.5~2014.7) (NSC 100-2220-E-009 -039) (PI)

Design and Optimization of Reconfigurable Communication Resources for Application Specific Multi-Core Systems (2010.08~2011.07) (NSC 99-2221-E-009-190) (PI)

Cross-Layer Co-Design Framework and Methodology for Multi-Core Systems (2009.11~2010.10) (NSC 98-2218-E-009-022) (PI)

Publications

Journals

1. Aman Sinha, Bo-Cheng Lai, Jhih-Yong Mai, "A Bin-based Indexing for Scalable Range Join on Genomic Data," IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2023. (to appear) 

2. Aman Sinha, Huei-Chun Yang, Pei-Yi Liu, Yen-Shi Kuo, Yuhao Fang, Tien-Shuo Chang, Ke-Han Li, Bo-Cheng Lai, "DSIM: Distributed Sequence Matching on Near-DRAM Accelerator for Genome Assembly," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Volume: 12, Issue: 2, pp. 486 - 499, June 2022. 

3. Abdelrahman Elabd, Vesal Razavimaleki, Shi-Yu Huang, Javier M Duarte, Markus Atkinson, Gage DeZoort, Peter Elmer, Jin-Xuan Hu, Shih-Chieh Hsu, Bo-Cheng Lai, Mark Neubauer, Isobel Ojalvo, Savannah Thais, "Graph Neural Networks for Charged Particle Tracking on FPGAs," Frontiers in Big Data, section Big Data and AI in High Energy Physics, Volume 5, 2022. (https://www.frontiersin.org/articles/10.3389/fdata.2022.828666/full)

4. Pham, D.-A.; Lai, B. -C.; "Dataflow and Microarchitecture Co-optimization for Sparse CNN on Distributed PE Accelerator," IET Circuits, Devices & Systems, Vol. 14, Issue:8, pp. 1185 – 1194, November 2020. 

5. Lai, B. -C.; Chen, C. -Y.; Hsin, Y. -D.; Lin, B. -Y.; "A Two-Directional BigData Sorting Architecture on FPGA," IEEE Computer Architecture Letters. Vol. 19, Issue:1, pp. 72-75, 2020.

6. Emara, M.; Lai, B. -C.; "Selective Bypassing and Mapping for Heterogeneous Applications on GPGPUs," Journal of Parallel and Distributed Computing, Elsevier, Volume 142, Pages 106-118,. August 2020.

7. Lai. B.-C.; Chen, B.-Y.; Chen, B.-E.; Hsin, Y.-D.; "REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory," IEEE Transactions on VLSI, Vol.28, Issue:3, pp.660-671, March 2020.

8. Lai. B.-C.; Pan, C.-W.; Lin, C.-Y.; "Enhancing Utilization of SIMD-like Accelerator for Sparse Convolutional Neural Networks," IEEE Transactions on VLSI, Vol.27 , Issue:5 , pp. 1218 - 1222, May 2019. 

9. Lai. B.-C.; Wu, T.-Y.; Chiu, T.-H.; Li, K.-C.; Lee, C.-Y.; Chien, W.-C.; W. H. Wong; "Towards High Performance Data Analytic on Heterogeneous Many-core Systems: A study on Bayesian Sequential Partitioning," Journal of Parallel and Distributed Computing, Elsevier. Volume 122, pp. 36-50, December 2018. 

10. Cheng, A.-T.; Chen, C.-Y.; Lai, B.-C.; , Lin, C.-H.; "Software and Hardware Enhancement of Convolutional Neural Networks on GPGPUs," Advances in Science, Technology and Engineering Systems Journal, Vol. 3, No. 2, 28-39, 2018.

11. Lai, B.C.; Huang, K.H.; "An Efficient Hierarchical Banking Structure for Algorithmic Multi-ported Memory on FPGA,"  IEEE Transactions on VLSI, Volume 25, Issue 10, pp.2776-2788, October 2017.

12. Lai, B.C.; Lin, J.L.; "Efficient Designs of Multi-ported Memory on FPGA," IEEE Transactions on VLSI, Volume: 25, Issue:1 pp. 139-150, January 2017. 

13. Lai, B.C.; Lee, C.Y.; Chiu, T.H.; Kuo, H.K.; Chang, C.K.; "Unified Designs for High-Performance LDPC Decoding on GPGPU," IEEE Transactions on Computers, Volume: 65, Issue: 12, pp. 3754-3765, December 2016. 

14. Lai, B.C.; Platero, L.G.; Kuo, H.K.; "A Quantitative Method To Data Reuse Patterns of SIMT Applications," IEEE Computer Architecture Letters, Volume: 15, Issue: 2, pp. 73-76, 2016. 

15. Lai, B.C.; Li, K.C.; Li, G.R.; Chiang, C.H.; "Self Adaptable Multithreaded Object Detection on Embedded Multicore Systems," Journal of Parallel and Distributed Computing, vol.78, pp.25–38, April 2015.

16. Pan, G.Y.; Lai, C.Y.; Jou, J.Y.; Lai, B.C.; "Power Efficient Instancy Aware DRAM Scheduling," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E98-A, No.4, April 2015.

17. Pan, G.Y.; Yang, J.; Jou, J.Y.; Lai, B.C.; “Scalable Global Power Management Policy Based-on Combinatorial Optimization for Multiprocessor Systems,” ACM Transactions on Embedded Computing Systems, 14(4), 1-24, December 2015. 

18. Lai, B.C.; Chen, K.T.; Wu, P.R.; "A High-Performance Double Layer Counting Bloom Filter for Multicore Systems," IEEE Transactions on VLSI, Volume 23, Issue 11, pp. 2473 - 2486, November 2015.

19. Lai, B.C.; Kuo, H.K.; and Jou, J.Y.; "A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs," IEEE Transactions on Computers, Volume 64, Issue 4, pp.884-898, April 2015.

20. Kuo, H.K.; Lai, B.C.; and Jou, J.Y.; “Reducing Contention in Shared Last-Level Cache for Throughput Processors,” ACM Transactions on Design Automation of Electronic Systems, Volume 20, Issue 1, No. 12, November 2014.

21. Pan, G.Y.; Jou, J.Y.; Lai, B.C.; "Scalable Power Management using Multi-Level Reinforcement Learning for Multiprocessors," ACM Transactions on Design Automation of Electronic Systems, Volume 19, Issue 4, No. 33, August 2014.

22. Chen, B.-Y., Lai, B.-C.C.; "A High-Performance Parallel Graph Cut Optimization for Depth Estimation," Smart Innovation, Systems, and Technologies, Volume 21, pp. 311 - 320, 2013.

23. Kim, J.; Lai, B.C.; Chang, M-C. F.; and Verbauwhede I.; "A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems," IEEE Transaction on Computers, 2008. 

24. Hwang, D.; Tiri, K.; Hodjat, A.; Lai, B.C.; Yang, S.; Schaumont, P.; and Verbauwhede, I.; "AES-Based Cryptographic and Biometric Security Coprocessor IC in 0.18-um CMOS Resistant to Side-Channel Power Analysis Attacks," Invited for the IEEE Journal of Solid State Circuits (JSSC), Special Issue on the 2005 Symposium on VLSI Circuits, 2005.

25. Chang, F.; Verbauwhede, I.; Chien, C.; Xu, Z.; Kim, J.; Ko, J.; Gu, Q.; Lai, B.C.; "Advanced RF / Baseband Interconnect Schemes for Inter- and Intra ULSI communications,” Invited for the IEEE Transaction on Electron Device (TED), 2005.  

Conferences

1. Bo-Han Li, Kuan-Chih Lin, Hao Zuo, Po-Cheng Pan, Hung-Ming Chen, Shyh-Jye Jou, Chien-Nan Jimmy Liu and Bo-Cheng Lai, "Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization," IEEE 67th International Midwest Symposium on Circuits and Systems (MWSCAS), August 2024. 

2. Aman Sinha, Shih-Chen Lo and Bo-Cheng Lai, "Accelerating Range Joins for Genomic Variant Annotation on HBM-enabled FPGA," Work-in-Progress (WIP) poster sessions at the 61th DAC, June 23-27, 2024. 

3. Yi-Ting Wu, Tzu-Yun Yen, Yu-Pei Lin, Bo-Cheng Lai, "HeteroEML: Heterogeneous Design Methodology of Edge Machine Learning on CPU+FPGA Platform," The 6th IEEE International Conference on Artificial Intelligence Circuits and Systems (IEEE AICAS 2024), April 22-25, 2024. 

4. Aman Sinha, Pei-Yi Liu, Yuhao Fang, Jhih-Yong Mai and Bo-Cheng Lai, "GRONA: A Framework for Gather-and-Reduce On Near-Memory Accelerators," 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2023), December 2023.

5. Xiao-han Liu, Chi-Jui Chen, Yan-Lun Huang, Ling-Chi Yang, Yi-hui Chen, Scott Hauck, Shih-Chieh Hsu, Elham E Khoda, Bo-Cheng Lai, "FPGA Deployment of LFADS for Real-time Neuroscience Experiments", 2023 International Conference on Computer-Aided Design (ICCAD), November 2023.

6. Shi-Yu Huang, Yun-Chen Yang, Yu-Ru Su, Bo-Cheng Lai, Javier Duarte, Scott Hauck, Shih-Chieh Hsu, Jin-Xuan Hu and Mark S. Neubauer, "Low Latency Edge Classification GNN for Particle Trajectory Tracking on FPGAs," 33rd International Conference on Field-Programmable Logic and Applications (FPL), September 2023. 

7. Aman Sinha, Yu-Hao Fang, Bo-Cheng Lai, "Regal : Reprogrammable Engines for Genome Analysis on LPDDR4x-Based Stacked DRAM," 2023 International Symposium on Circuits and Systems (ISCAS), June 2023.

8. Aman Sinha, Jhih-Yong Mai, Bo-Cheng Lai, "MSIM: A Highly Parallel Near-Memory Accelerator for MinHash Sketch," IEEE International System-on-Chip Conference (SOCC), September 2022.

9. Yu-Hao Fang, Aman Sinha, Bo-Cheng Lai, "REAL-GSM : Re-programmable Engines for Acceleration on LPDDR4x-based Stacked DRAM to support Genomic String Matching," 4th HPCA Workshop on ACCELERATOR ARCHITECTURE IN COMPUTATIONAL BIOLOGY AND BIOINFORMATICS, June 2022. 

10. Po-Yen Lin, Yen-Shi Kuo, Bo-Cheng Lai, "A Highly Parallel Fine-Grained Sort-Merge Join On Near Memory Computing," 2022 International Symposium on Circuits and Systems (ISCAS), June 2022. 

11. Bo-Rong Yen, Rios Edwin Arkel, Bo-Cheng Lai, "DLPrPPG: Development and Design of Deep Learning Platform for Remote Photoplethysmography," 2022 International Symposium on Circuits and Systems (ISCAS), June 2022. 

12. Rios Edwin Arkel, Bo-Cheng Lai, "Anime Character Recognition using Intermediate Features Aggregation," 2022 International Symposium on Circuits and Systems (ISCAS), June 2022. 

13. Yi-Da Hsin; Yen-Shi Kuo; Bo-Cheng Lai, "Distributed Sorting Architecture on Multiple FPGA," 2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2022. [Best Paper Award]

14. Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu and Shyh-Jye Jou, "DASC : A DRAM Data Mapping Methodology for  Sparse Convolutional Neural Networks," 2022 Design, Automation and Test in Europe Conference (DATE), March 2022. 

15. Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou, "On Reconfiguring Memory-Centric AI Edge Devices for CIM," 2021 International SoC Design Conference (ISOCC), October 2021.

16. Hsin, Yi-Ta; Lai, B.-C.; "Design of Distributed Sorting Accelerator on Multiple FPGAs", 2021 VLSI Design / CAD Symposium, August 2021. 

17. Rios, Edwin Arkel; Lai C.-C.; Yan, B.-R.; Lai, B.-C.; "Parametric Study of Performance of Remote Photopletysmography System," IEEE International Symposium on Circuits and Systems (ISCAS), May 2021. 

18. Chen, B.-E.; Chen, B.-Y.; Lai, B.-C.; " Reconfigurable Database Processor for Query Acceleration on FPGA," International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), April 2021.

19. Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu and Shyh-Jye Jou, "On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications," International Conference On Computer Aided Design (ICCAD), November 2020.

20. Sinha, A.; Lai, B.-C.; "A Bin-based Indexing for Scalable Range Join on Genomic Data," Design Automation Conference (DAC), Work-In-Progress Session, July 2020.

21. Sinha, A.; Lai, B.-C.; "DP2: A Highly Parallel Range Join for Genome Analysis on Distributed Computing Platform," the 2019 International Conference on High Performance Computing & Simulation (HPCS 2019), July 2019. 

22. Tseng, W.-F.; Lai, B.-C.; Pan, C.-W.; "Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Network," 2019 IEEE International Conference on Applied System Innovation, April 2019. 

23. Chen, B.-Y.; Chen, B.-E.; Lai, B.-C; "Efficient Write Scheme for Algorithm-based Multi-ported Memory," International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), April 2019. [Best Paper Nominee]

24. Chen, C.-C.; Lee, Y.-J.; Yang, C.-L.; Lai, B.-C.; "Analytical Framework for Locality Optimization in CNN," Design Automation Conference (DAC), Work-In-Progress Session, June 2018. 

25. Lin, C.-Y.; Lai, B.-C; "Supporting Compressed-Sparse Activations and Weights on SIMD-like Accelerator for Sparse Convolutional Neural Networks," The 23rd IEEE International Symposium on Asia and South Pacific Design Automation Conference (ASP-DAC), January 2018. 

26. Lin, C.-H.; Cheng, A.-T.; Lai, B.-C.; "A Software Technique to Enhance Register Utilization of Convolutional Neural Networks on GPGPUs," IEEE International Conference on Applied System Innovation, May 2017. [Best Paper Award]

27. Chen, S.-Y.; Wei, C.-I.; Chiu, Y.-C.; Lai, B.-C.; "A Hadoop-based Principle Component Analysis on Embedded Heterogeneous Platform," International Symposium on VLSI Design, Automation, and Test (VLSI-DAT),  April 2017.

28. Tseng, Y.L.; Huang, K.H.; Lai, B.C.; "Scalable Mutli-Layer Barrier Synchronization on NoC," International Symposium on VLSI Design, Automation, and Test (VLSI-DAT),  April 2016.

29. Wu, P.J.; Lin, C.Y.; Lai, B.C.; "Design of Application Specific Throughput Processor for Matrix Operations," The 18-th International Conference on Network-Based Information Systems (NBiS), September 2015. 

30. Lee, J.Y.; Wang, Y.T.; Lai, B.C.; "Computation and Communication Aware Task Graph Scheduling on Multi-GPU Systems," IEEE International Conference on Digital Signal Processing, July 2015.

31. Lin, J.L. and Lai, B.C.; "BRAM Efficient Multi-ported Memory on FPGA," International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), April. 2015.

32. Pan, G.Y.; Lai, B.C.; and Jou, J.Y.; “A Learning-on-Cloud Power Management Policy for Smart Devices,” IEEE/ACM The International Conference on Computer-Aided Design (ICCAD), pp.376-381, November 2014.

33. Tseng, Y.Y.; Huang, Y.H.; Lai, B.C.; and Lin, J.L. "Automatic Data Layout Transformation for Heterogeneous Many-core Systems,"  the 11th IFIP International Conference on Network and Parallel Computing (NPC-14), September 2014. 

34. Lai, B.C.; Yen, T.K.; Yu, B.Y.; "A Cache Aware Multithreading Decision Scheme on GPGPUs," The 8th IEEE 8th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-14), September 2014. 

35. Lu, C.F.; Kuo, H.K.; Lai, B.C.; and Jou, J.Y.; "A Combined Data Reuse and Cache Utilization Scheduling Algorithm for Throughput Processors," Design Automation Conference (DAC), Work-In-Progress Session, June 2014. 

36. Yu-Hao Huang, Ying-Yu Tseng, Hsien-Kai Kuo, Ta-Kan Yen and Bo-Cheng Charles Lai, "A Locality-Aware Dynamic Thread Scheduler for GPGPUs", 14'th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT'13), December 16-18, 2013.

37. Hao-Wei Liu, Hsien-Kai Kuo, Kuan-Ting Chen, Bo-Cheng Lai, "Memory Capacity Aware Non-Blocking Data Transfer on GPGPU", SiPS 2013.

38. Yen, T.K.; Kuo, H.K.; Lai, B.-C.C. "A distributed thread scheduler for dynamic multithreading on throughput processors",  International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), pp.1-4, April. 2013 .

39. Kuo, H.K.;  Yen, T.K.; Lai, B.-C.C. J.Y. Jou, "Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs", Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 338-343, Jan. 2013.

40. Chen, B.Y.; Lai, B.C.; " A High-Performance Parallel Graph Cut Optimization For Depth Estimation", Proceedings of the International Computer Symposium (ICS), pp.311-320, Dec. 2012.

41. Chiu, T.H.; Kuo, H.K.; Lai, B.C.; "A Highly Parallel Design for Irregular LDPC Decoding on GPGPUs", Asia-Pacific Signal & Information Processing Association Annual Summit and Conference (APSIPA ASC), pp.3-6, Dec. 2012.

42. Chen, K.T.; Wu, P.R.; Lai, B.C.; "Reduce Data Coherence Cost with An Area Efficient Double Layer Counting Bloom Filter",  International Symposium on Parallel Architectures, Algorithms and Programming, pp.7-12, Dec. 2012.

43. Li, G.R.;  Lai, B.C.; " A Highly Parallel Design of Image Surface Layout Recovering on GPGPU", IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp.1-4, April 2012.

44. Kuo, H.K.; Chen, K.T.; Lai, B.C.; Jou, J.Y.; "Thread Affinity Mapping for Irregular Data Access on Shared Cache GPGPU", The 17th IEEE International Symposium on Asia and South Pacific Design Automation Conference (ASP-DAC), pp.659-664, January 2012.

45. Lai, B.C.; Chiang, C.H.; Li, G.R.; "Classifier Grouping to Enhance Data Locality for A Multi-Threaded Object Detection Algorithm", The 17th IEEE International Conference on Parallel and Distributed Systems (ICPADS 2011), December 2011. 

46. Lai, B.C.; Chiang, C.H.; Li, G.R.; "Data Locality Optimization for A Parallel Object Detection On Embedded Multi-Core Systems", The 2nd IEEE International Conference on Software Engineering and Service Sciences, pp.576-579, July 2011. 

47. Chiang, C.H.; Kao, C.H.;  Li, G.R.; Lai, B.C.;"Multi-Level Parallelism Analysis of Face Detection on a Shared Memory Multi-Core System", IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp.1-4, April 2011.

48. Chen, W.J.; Kuo, H.K.; Chiu, T.H.; Lai, B.C.;"FDPrior: A Force-Directed Based Parallel Partitioning Algorithm for Three Dimensional Integrated Circuits on GPGPU", IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp.1-4, April 2011. 

49. Yen, T.K.; Lai, B.C.;"Fast Parallel Analysis of Dynamic Contrast-Enhanced Magnetic Resonance Imaging on GPGPU", in ICS, pp.927-930, Dec. 2010.

50. Kuo, H.K.; Lai, B.C.; Jou, J.Y.; “Unleash the Parallelism of 3DIC Partitioning On GPGPU,” in SOC Conference, pp. 127-132, Sept. 2010.

51. Lai, B.C.; Schaumont, P.; Qin, W.; Verbauwhede, I.; "Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip,” IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 15-18, September 2006.

52. Lai, B.C.; Schaumont, P.; Verbauwhede, I.; "A Light-Weight Cooperative Multithreading with Hardware Supported Thread-Management on an Embedded Multi-Processor System,” Thirty-Ninth Annual Asilomar Conference on Signals, Systems, and Computers, pp. 1647–1651, November 2005.

53. Lai, B.C.; Schaumont, P.; Verbauwhede, I.; "Energy and Performance Analysis of Mapping Parallel Multi-threaded Tasks for An On-Chip Multi-Processor System,” IEEE International Conference on Computer Design (ICCD), pp.102-104, October 2005.

54. Schaumont, P.; Lai, B.C.; Qin, W.; Verbauwhede, I.; "Cooperative Multithreading on Embedded Multiprocessor Architectures Enables Energy-Scalable Design,” Proceeding 2005 Design Automation Conference (DAC), pp. 27-30, June 2005.

55. Tiri, K.; Hwang, D.; Hodjat, A.; Lai, B.C.; Yang, S.; Schaumont, P.; and Verbauwhede, I.; "Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment," Proceedings of Workshop on Cryptographic Hardware and Embedded Systems (CHES 2005), pp. 354-365, August 2005. 

56. Tiri, K.; Hwang, D.; Hodjat, A.; Lai, B.C.; Yang, S.; Schaumont, P.; and Verbauwhede, I.; "AES-Based Cryptographic and Biometric Security Coprocessor IC in 0.18-um CMOS Resistant to Side-Channel Power Analysis Attacks," Proceedings of Symposia on VLSI Technology and Circuits (VLSI SYMPOSIUM 2005), pp. 216-219, June 2005. 

57. Tiri, K.; Hwang, D.; Hodjat, A.; Lai, B.C.; Yang, S.; Schaumont, P.; and Verbauwhede, I.; "A Side-Channel Leakage-Free Coprocessor IC in 0.18um CMOS for Embedded AES-based Cryptographic and Biometric Processing," IEEE Proceedings of 42nd Design Automation Conference (DAC 2005), pp. 222-227, June 2005. (Winner DAC/ISSCC 2005 Student Design Contest 3rd place operational category) 

58. Hodjat, A.; Hwang, D.; Lai, B.C.; Tiri, K.; and Verbauwhede, I.; “A 3.84 Gbits/s AES Crypto Coprocessor with Modes of Operation in a 0.18-um CMOS Technology”, Proceedings of IEEE Great Lake Symposium on VLSI (GLSVLSI 2005), pp. 60-63, April 2005.

59. Lai, B.C.; Schaumont, P.; Verbauwhede, I.; "CT-Bus: A heterogeneous CDMA/TDMA bus for future SOC,” Thirty-Eighth Annual Asilomar Conference on Signals, Systems, and Computers, pp. 1868-1872, November 2004.

60. Hwang, D.; Lai, B.C.; Verbauwhede, I.; "Energy-memory-security trade-offs in distributed sensor networks,” Proceeding 3rd International Conference on Ad-Hoc Networks and Wireless (ADHOC-NOW), Springer-Verlag LNCS 3158, pp. 70-81, July 2004.

61. Lai, B.C.; Hwang, D.; Kim, S.; Verbauwhede, I.; "Reducing radio energy consumption of key management protocols for wireless sensor networks,” Proceeding ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), pp. 351-356, August 2004.

62. Schaumont, P.; Sakiyama, K.; Fan, Y.; Hwang, D.; Yang, S.; Hodjat, A.; Lai, B.C.; Verbauwhede, I.; "Testing ThumbPod: softcore bugs are hard to find", Proceedings of 8th High-Level Design Validation and Test Workshop (HLDVT 2003), pp. 77-82, November 2003. 

63. Hwang, D.; Schaumont, P.; Fan, Y.; Hodjat, A.; Lai, B.C.; Sakiyama, K.; Yang, S.;  Verbauwhede I.; "Design flow for HW / SW acceleration transparency in the ThumbPod secure embedded system", IEEE Proceedings of 40th Design Automation Conference (DAC 2003), pp. 60-65, June 2003. (Winner of DAC/ISSCC 2003 Student Design Contest, Honorable mention in conceptual category) 

64. Tuan, T.; Lai, B.C.; "Leakage Power Analysis of a 90nm FPGA,” IEEE Custom Integrated Circuits Conference (CICC), pp.57-60, September 2003.      

Patents

1. Lin, C.-Y.; Lai, B.-C.; "APPARATUS AND METHOD OF USING DUAL INDEXING IN INPUT NEURONS AND CORRESPONDING WEIGHTS OF SPARSE NEURAL NETWORK." U.S. Patent Application US 15/594,667, Nov. 2018.

2. Lai, B.-C.; Chiu, T.-C.; "LOW-DENSITY PARITY CHECK DECODING METHOD PERFORMING ON GENERAL GRAPHIC PROCESSING UNIT AND DECODING APPARATUS." U.S. Patent No. 9,973,214, May. 2018.

3. Lu, K.-C; Lai, B.-C; Huang, K.-H; Lin, J.-L; "METHOD OF ACCESSING MULTI-PORT MEMORY MODULE, METHOD FOR INCREASING WRITE PORTS OF MEMORY MODULE AND ASSOCIATED MEMORY CONTROLLER." U.S. Patent Application US 15/098,330, Oct. 2016.

4. Lai, B.-C; Lin, J.-L; Lu, K.-C; "METHOD FOR ACCESSING MULTI-PORT MEMORY MODULE AND ASSOCIATED MEMORY CONTROLLER." U.S. Patent Application US 15/ 098,336, Oct. 2016.

Book Chapters

• Verbauwhede, I., Hodjat, A., Hwang, D. and Lai, B.C., "Security for Ambient Intelligent Systems" Book Chapter in Ambient Intelligence, Springer-Verlag, Part II System Design, and Architecture, pp. 199-221, 2005.