News

2022-8 彥希 passes his Master Oral Defense. Congratulations!
2022-7 Our work, "MSIM: A Highly Parallel Near-Memory Accelerator for MinHash Sketch" is accepted by SOCC 2022.
2022-7 鈺豪 passes his Master Oral Defense. Congratulations!
2022-6 Our work, "REAL-GSM : Re-programmable Engines for Acceleration on LPDDR4x-based Stacked DRAM to support Genomic String Matching" is accepted by AACBB 2022.
2022-5 Our work, "DSIM: Distributed Sequence Matching on Near-DRAM Accelerator for Genome Assembly" is accepted by JETCAS 2022.
2022-1 Our work, "A Highly Parallel Fine-Grained Sort-Merge Join On Near Memory Computing" is accepted by ISCAS 2022.
2022-1 Our work, "DLPrPPG: Development and Design of Deep Learning Platform for Remote Photoplethysmography."" is accepted by ISCAS 2022.
2022-1 Our work, "Anime Character Recognition using Intermediate Features Aggregation" is accepted by ISCAS 2022.
2022-1 沛宜 passes his Master Oral Defense. Congratulations!
2021-12 柏融passes his Master Oral Defense. Congratulations!
2021-11 Our work, "A Distributed Sorting Architecture on Multiple FPGA" is accepted by VLSI-DAT 2022.
2021-11 佾達 passes his Master Oral Defense. Congratulations!
2021-11 博彥 passes his Master Oral Defense. Congratulations!
2021-11 Our work, "DASC : A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks" is accepted by DATE 2022.
2021-10 Our work, "On Reconfiguring Memory-Centric AI Edge Devices for CIM" is accepted by ISOCC 2021.
2021-7 柏伸 passes his Master Oral Defense. Congratulations!

2021-7 子杰 passes his Master Oral Defense. Congratulations!

2021-6 卉淳 passes her Master Oral Defense. Congratulations!

2021-5 Himadri passes his Master Oral Defense. Congratulations!

2020-12 Our work, " Reconfigurable Database Processor for Query Acceleration on FPGA " is accepted by VLSI-DAT 2021.

2020-7 博恩passes his Master Oral Defense. Congratulations!

2020-6 Our work, " Design Analysis Of High Level Synthesis For Big Data Engines On FPGA" is accepted by VLSI-CAD 2020.

2019-7 Our work, "DP2: A Highly Parallel Range Join for Genome Analysis on Distributed Computing Platform" is accepted by International Conference on High Performance Computing & Simulation (HPCS) 2019.

2019-4 Our work, "Increasing PE Utilization with a SW/HW Co-Design Technique for Sparse Convolutional Neural Network (CNN)" is accepted by ICASI 2019.

2019-4 Our work, "Efficient Write Scheme for Algorithmic-based Multi-ported Memory" is accepted by VLSI-DAT 2019.

2019-4 昌逸 and 安庭 passes their Master Oral Defense. Congratulations!

2019-3 于真 passes her Master Oral Defense. Congratulations!

2019-2 柏亞 passes his Master Oral Defense. Congratulations!

2019-1 Our work, "Enhancing Utilization of SIMD-like Accelerator for Sparse Convolutional Neural Networks (CNNs)" is accepted by IEEE Transactions on VLSI (TVLSI) 2019.

2018-7 Our work, "Towards High Performance Data Analytic on Heterogeneous Many-Core Systems: A Study on Bayesian Sequential Partitioning (BSP)" is accepted by Journal of Parallel and Distributed Computing, Elsevier [Online 2018].

2018-7 俊瑋 passes his Master Oral Defense. Congratulations!

2018-6 Our work, "Analytical Framework for Locality Optimization in CNNs (Convolutional Neural Networks)" is accepted by Design Automation Conference (DAC) 2018.

2018-3 峻楓 passes his Master Oral Defense. Congratulations!

2018-2 Our work, "Software and Hardware Enhancement of Convolutional Neural Networks on GPGPUs" is accepted by ASTES (Advances in Science, Technology and Engineering Systems) 2018.

2018-1 Duc-An (范德安) passes his Master Oral Defense. Congratulations!

2018-1 Our work, "Supporting Compressed-Sparse Activations and Weights on SIMD-like Accelerator for Sparse Convolutional Neural Networks (CNNs)" is accepted by ASP-DAC 2018.

2017-7 Our work, "An Efficient Hierarchical Banking Structure for Algorithmic Multi-Ported Memory on FPGAs", is accepted by IEEE Transactions on VLSI (TVLSI) 2017.

2017-6 品彰 passes his Master Oral Defense. Congratulations!

2017-5 建宇 passes his Master Oral Defense. Congratulations!

2017-5 Our work, "A Software Technique to Enhance Register Utilization of Convolutional Neural Networks (CNNs) on GPGPUs", is accepted by IEEE International Conference on Applied System Innovation.

2017-4 Our work, "A Hadoop-base Principle Component Analysis on Embedded Heterogeneous Platform", is accepted by VLSI-DAT 2017.

2017-1 Our work, "Efficient Designs of Multi-Ported Memory on FPGAs", is accepted by IEEE Transactions on VLSI (TVLSI).

2016-12 Our work, "Unified Designs for High-Performance LDPC Decoding on GPGPUs", is accepted by IEEE Transactions on Computers (TC).

2016-9 子豪 passes his Master Oral Defense. Congratulations!

2016-8 哲懷 passes his Master Oral Defense. Congratulations!

2016-7 琨驊 and Moustafa (毛沙敏) passes their Master Oral Defense. Congratulations!

2016-4 Our work, "Scalable Multi-Layer Barrier Synchronization on NoC", is accepted by VLSI-DAT 2016.

2016-4 Our work, "A Quantitative Method To Data Patterns of SIMT Applications", is accepted by IEEE Computer Architecture Letters.

2015-9 Our work, "Design of Application Specific Throughput Processor for Matrix Operations", is accepted by The 18-th International Conference on Network-Based Information Systems (NBiS).

2015-8 柏堯, 于倫, 俊良, 聖諺, and 佳穎 passes their Master Oral Defense. Congratulations!

2015-7 Our work, "Computation and Communication Aware Task Graph Scheduling on Multi-GPU Systems", is accepted by IEEE International Conference on Digital Signal Processing.

2015-4 Our work, "Self Adaptable Multithreaded Object Detection on Embedded Multicore Systems", is accepted by Journal of Parallel and Distributed Computing.

2015-4 Our work, "Power Efficient Instancy Aware DRAMs Scheduling", is accepted by IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences.

2015-4 Our work, "BRAMs efficient multi-ported memory on FPGAs", is accepted by VLSI-DAT 2015.

2014-11 Our work, "Scalable Global Power Management Policy Based-on Combinatorial Optimization for Multiprocessor Systems", is accepted by ACM Transactions on Embedded Computing Systems.

2014-11 Our work, "A Learning-on-Cloud Power Management Policy for Smart Devices", is accepted by IEEE/ACM The International Conference on Computer-Aided Design (ICCAD).

2014-11 Our work, "A High-Performance Double Layer Counting Bloom Filter for Multicore Systems", is accepted by IEEE Transactions on VLSI (TVLSI).

2014-6 秉儒 and 允廷 passes his Master Oral Defense. Congratulations!

2014-6 Our work, "A Cache Aware Multithreading Decision Scheme on GPGPUs", is accepted by The 8th IEEE 8th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSoC-14).

2014-6 Our work, "Automatic Data Layout Transformation for Heterogeneous Many-core Systems", is accepted by the 11th IFIP International Conference on Network and Parallel Computing.

2014-5 Our work, "Reducing Contention in Shared Last-Level Cache for Throughput Processors", is accepted by ACM Transactions on Design Automation of Electronic Systems.

2014-5 玹凱 passes his Ph.D. Oral Defense. Congratulations!

2014-4 坤駿 passes his Master Oral Defense. Congratulations!

2014-3 智恆 and 大剛 passes their Master Oral Defense. Congratulations!

2014-1 Our work, "A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs", is accepted by IEEE Transactions on Computers (TC).

2013-9 Our work, "A Locality-Aware Dynamic Thread Scheduler for GPGPUs", is accepted by PDCAT 2013.

2013-7 奏翰, 柏諺, and Luis (盧以斯) passes their Master Oral Defense. Congratulations!

2013-7 Our work, "Memory Capacity Aware Non-Blocking Data Transfer On GPGPUs", is accepted by SiPs 2013.

2013-7 Our work, "A High-Performance Depth Map Optimization on Heterogeneous Many-core Systems", is accepted by VLSI-CAD 2013.

2013-4 Our work, "A Distributed Thread Scheduler for Dynamic Multithreading on Throughput Processors", is accepted by VLSI-DAT 2013.

2012-12 Our work, "Reduce Data Coherence Cost with An Area Efficient Double Layer Counting Bloom Filter", is accepted by APSIPA 2012.

2012-10 Our Work, "A High-Performance Parallel Graph Cut Optimization For Depth Estimation", is accepted by ICS 2012.

2012-9 冠儒 passes his Master Oral Defense. Congratulations!

2012-9 Our Work, "Cache Capacity Aware Thread Scheduling for Irregular Memory Access on Many-Core GPGPUs", is accepted by ASP-DAC 2013.

2012-9 Our Work, "Reduce Data Coherence Cost with An Area Efficient Double Layer Counting Bloom Filter", is accepted by PAAP 2012.

2012-9 Our Work, "A Highly Parallel Design for Irregular LDPC Decoding on GPGPUs", is accepted by APSIPA 2012.

2012-1 Our Work, "A Highly Parallel Design of Image Surface Layout Recovering on GPGPUs", is accepted by VLSI-DAT 2012.

2011-9 彥凱 received an "Outstanding Achievement Award" on the Altera Design Contest (ADC) 2011.

2011-9 Our work, "Thread Affinity Mapping for Irregular Data Access on Shared Cache GPGPUs", is accepted by ASP-DAC 2012.

2011-9 彥凱 project goes into the final of Altera Design Contest (ADC) 2011.

2011-9 奏翰 and 冠儒 receive the outstanding "TA awards" for their endeavors to the teaching on Logic Design in spring 2011.

2011-9 Our work on Multi-threaded Object Detection Algorithm is accepted by ICPADS 2011.

2011-8 琬菁 and 志軒 passes their Master Oral Defense. Congratulations!

2011-7 Our work, "Data Locality Optimization for A Parallel Object Detection On Embedded Multi-Core Systems", is presented on ICSESS 2011.

2011-1 Our work, "Multi-Level Parallelism Analysis of Face Detection on a Shared Memory Multi-Core Systems", is accepted by VLSI-DAT 2011.

2011-1 Our work, "FDPrior: A Force-Directed Based Parallel Partitioning Algorithm for Three Dimensional Integrated Circuits on GPGPUs", is accepted by VLSI-DAT 2011.