Research Interests
FET Biosensor : Design and Simulation
Ultra Low Power VLSI Circuits
AI/ML-VLSI
Emerging Device Modelling
Manash Chanda Resume
docs.google.com/document/d/1AV6tPfOvvIikMeDkppLG5oVlQRX4qRlnS4epvEjRLTQ/edit
- Google Scholar ID (case sensitive) : iKAoUssAAAAJ
List of Publications in Journals & Transaction :
2024:
Amit Bhattacharyya, Ayush Sarkar, Swapnendu Sarkar, Srishti Das, Soumyadeep Ghosh, Papiya Debnath, Debashis De and Manash Chanda, ""Charge Plasma persuaded underlapping dielectric modulated bio-tunnel FET realizing the steric repulsive effect.", Nano World Journal, Scopus indexed journal ( Scopus ID: 21100926589 ), Jan 2024
Mainak Mukherjee, Niloy Ghosh, Papiya Debnath, A Sarkar, MANASH CHANDA , "Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications " Accepted in Journal of Integrated Circuit and System, Vol. 19 No. 1 (2024), https://doi.org/10.29292/jics.v19i1.796
Amit Bhattacharyya, Debashis De, Manash Chanda," Reliability aspects in repulsive steric hindrance approach: Selectivity and sensitivity investigations", Micro and Nanostructures, 2024,207828,ISSN 2773-0123,https://doi.org/10.1016/j.micrna.2024.207828.
2023:
Adrija Mukherjee, Papiya Debnath, D. Nirmal, Manash Chanda, "A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications," Microelectronics Journal, 2023, 105689, ISSN 0026-2692, https://doi.org/10.1016/j.mejo.2023.105689.
Suman Sarkar, Papiya Debnath, Debashis De and Manash Chanda, “ A DFT Based Approach for NO2 Sensing Using Vander wall Hetero Monolayer”, IETE Journal of Research, Taylor and Fracsis. DOI:10.1080/02564602.2022.2143916
Adrija Mukherjee, Papiya Debnath & Manash Chanda (2023) Machine learning-based output prediction of negative capacitance tunnel-FET, International Journal of Electronics, DOI: 10.1080/00207217.2023.2224077 .
Suman Sarkar, Papiya Debnath, Debashis De & Manash Chanda (2023) A DFT Based Approach to Sense the SF6 Decomposed Gases Using Ni-doped WS2 Monolayer, IETE Technical Review, 40:5, 621-631, DOI: 10.1080/02564602.2022.2143916 .
S. Majumder, S. Bhattacharya, P. Debnath, B. Ganguly & M. Chanda (2023) Identification and classification of arrhythmic heartbeats from electrocardiogram signals using feature induced optimal extreme gradient boosting algorithm, Computer Methods in Biomechanics and Biomedical Engineering, DOI: 10.1080/10255842.2023.2265009
M. Chanda, S. D. Patel, A. Bhattacharyya and S. Sahay, "Impact of Transport Mechanism on Binding Kinematics and Sensitivity of FET Biosensors," in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2023.3281539.
A. Bhattacharyya, D. De and M. Chanda, "Ovarian-Cancer Biomarker (HE4) Recognition in Serum Using Hetero TFET Biosensor," in IEEE Transactions on Nanotechnology, vol. 22, pp. 238-244, 2023, doi: 10.1109/TNANO.2023.3272926.
T. Ganguli, M. Chanda and A. Sarkar, "Impact of Aspect Ratio and Interface Trap Charge on the Performances of Junctionless MOSFET-Based Adiabatic Logic Circuit," in IEEE Transactions on Electron Devices, vol. 70, no. 12, pp. 6157-6162, Dec. 2023, doi: 10.1109/TED.2023.3327348.
P Sriramani and N Mohankumar and Y Prasamsha and Angsuman Sarkar and Manash Chanda, "Threshold and surface potential-based sensitivity analysis of symmetrical double gate AlGaN/GaN MOS-HEMT including capacitance effects for label-free biosensing", Physica Scripta,vol. 98, no. 11, pp. 11506, doi:/10.1088/1402-4896/acff8e
2022:
Amit Bhattacharya, Debasish De, and Manash Chanda, "Sensitivity Measurement for Bio-TFET Considering Repulsive Steric Effects With Better Accuracy," IEEE TNANO, (DOI: 10.1109/TNANO.2022.3148922 ).
A. Bhattacharyya, Debashis De and Manash Chanda, "Temperature Imposed Sensitivity Issues of Hetero-TFET Based pH Sensor," in IEEE Transactions on NanoBioscience, 2022, doi: https://doi.org/10.1109/TNB.2022.3202242
Das, R., Chattopadhyay, A., Chanda, M. et al. "Analytical Modeling of Sensitivity Parameters Influenced by Practically Feasible Arrangement of Bio-Molecules in Dielectric Modulated FET Biosensor". Silicon (2022). DOI: https://doi.org/10.1007/s12633-021-01617-z.
T. Ganguli, M. Chanda, and A. Sarkar "Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime", Computers and Electrical Engineering, Volume 100, 2022, 107914, ISSN 0045-7906, https://doi.org/10.1016/j.compeleceng.2022.107914
G. Jana, D. Sen, P. Debnath and M. Chanda, "Power and delay analysis of dielectric modulated dual cavity Junctionless double gate field effect transistor based label-free biosensor", Computers and Electrical Engineering, Volume 99, 2022, 107828, ISSN 0045-7906. DOI: https://doi.org/10.1016/j.compeleceng.2022.107828
Mukherjee, M., Guha, S., Debnath, P. et al. "Analytical Modelling of Dopingless (DL) Impact Ionization MOSFET (IMOS)". Silicon (2022). https://doi.org/10.1007/s12633-022-01882-6.
Suman Sarkar, Papiya Debnath, Debashis De & Manash Chanda (2022) "A DFT Based Approach to Sense the SF6 Decomposed Gases Using Ni-doped WS2 Monolayer", IETE Technical Review, DOI: 10.1080/02564602.2022.2143916
Debarati Dey Roy, Pradipta Roy, Manash Chanda, Debashis De,"Ultra-low voltage adenine based gas sensor to detect H2 and NH3 at room temperature: First-principles paradigm" , International Journal of Hydrogen Energy, 2022, ISSN 0360-3199, https://doi.org/10.1016/j.ijhydene.2022.11.040.
Karmakar, Ananya & De, Arpan & Sen, Dipanjan & Chanda, Manash. (2022). "Design and Investigation of Double Gate Field Effect Transistor Based H2 Gas Sensor Using Ultra-Thin Molybdenum Disulfide". 10.21203/rs.3.rs-1611969/v1.
Ananya Karmakar, Adrija Mukherjee, Dipanjan Sen and Manash Chanda, "A junctionless dual-gate MOSFET-based programmable inverter for secured hardware applications using nitride charge trapping", Semicond. Sci. Technol., vol. 37, 115013, DOI 10.1088/1361-6641/ac92a3.
2021:
Shreya Bhattacharyya; Souvik Majumder; Papiya Debnath; Manash Chanda. "Arrhythmic Heartbeat Classification Using Ensemble of Random Forest and Support Vector Machine Algorithm". IEEE Transactions on Artificial Intelligence. May 2021. , (DOI:10.1109/TAI.2021.3083689 ).
Ankush Chattopadhyay, Manash Chanda, Chayanika Bose, C. K. Sarkar, “Analytical modeling of Linearity and Intermodulation distortion of 3D Gate All Around Junctionless (GAA - JL) FET”, Volume 150, February 2021, 106788, Superlattices and Microstructures, Elsevier, (DOI: https://doi.org/10.1016/j.spmi.2020.106788).
Ankush Chattopadhyay, Manash Chanda, Chayanika Bose, C. K. Sarkar"Analysis of Harmonic Distortions in GAA Junctionless FET using Analytical Model for reliable low power applications", accepted in Journal of Electronic Materials, Springer (Impact Factor 1.774 )
Sen, D., Sengupta, S.J., Roy, S. et al. Analysis of D.C Parameters of Short-Channel Heterostructure Double Gate Junction-Less MOSFET Circuits Considering Quantum Mechanical Effects. Silicon 13, 1165–1175 (2021). https://doi.org/10.1007/s12633-020-00507-0
2020:
Amit Bhattacharya, Manash Chanda and Debasish De “Analysis of Partial Hybridization and Probe Positioning on Sensitivity of a Dielectric Modulated Junctionless Label Free Biosensor”, IEEE Transaction on Nanoelectronics, vol. 19, pp. 719 – 727, 22 Sept. 2020, ( DOI: 10.1109/TNANO.2020.3025544).
Amit Bhattacharya, Manash Chanda and Debasish De “Analysis of Noise-Immune Dopingless Heterojunction Bio-TFET Considering Partial Hybridization Issue”, IEEE Transaction on Nanoelectronics, vol. 19, pp. 769 – 777, 26 Oct. 2020, ( DOI: 10.1109/TNANO.2020.3033966).
Amit Bhattacharyya, Manash Chanda and Debashis De, “GaAs0.5Sb0.5/ In0.53Ga0.47As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement”, Superlattices and Microstructures(Elsevier), Volume 142, June 2020, 106522 Impact Factor:2.117, (DOI: doi.org/10.1016/j.spmi.2020.106522).
Avtar Singh, Saurabh Chaudhury, Manash Chanda and Chandan Kumar Sarkar, “Split gated silicon nanotube FET for bio-sensing applications”, IET Circuit, Device and System, 23rd Nov 2020, Early Access, ( DOI: 10.1049/iet-cds.2020.0208).
Swarnil Roy, Gargi Jana and Manash Chanda, “Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application”, Silicon, Springer Nature B.V. 2020, Accepted For Publication. ( DOI: http://dx.doi.org/10.1007/s12633-020-00870-y).
Dipanjan Sen, Savio Sengupta, Manash Chanda, Swarnil.Roy (2020). Analysis of D.C Parameters of Short-Channel Heterostructure Double Gate Junction-Less MOSFET Circuits Considering Quantum Mechanical Effects. Silicon, Springer, ( DOI: 12. 10.1007/s12633-020-00507-0) .
Mainak Mukhrjee, Manash Chanda and Angsuman Sarkar and Anup Dey, “Effect of band non-parabolicity on energy sub-band profile for nano-dimensional MOSFET”, Journal of Microsystem Technologies, Springer, pp. 1-8, Feb, 2020. [SCI, Impact factor: 1.6] ( DOI: 10.1007/s00542-020-04761-5) .
Ruben Ray, Rahul Das and Manash Chanda, “Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET” Journal of Microsystem Technologies, Springer, Feb, 2020. [SCI, Impact factor: 1.6], ( DOI: 10.1007/s00542-020-04765-1).
2019:
Amit Bhattacharya, Manash Chanda and Debasish De, "Performance Assessment of New Dual-Pocket Vertical Hetero-structure Tunnel FET-Based Biosensor Considering Steric Hindrance Issue", IEEE Transaction on Electron Device, (DOI: 10.1109/TED.2019.2928850).
Arighna Basak, Manash Chanda and Angsuman Sarkar, “Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications”, Journal of Microsystem Technologies, Springer, Nov, 2019, [SCI, Impact factor: 1.6],( DOI: doi.org/10.1007/s00542-019-04691-x).
Dipanjan Sen, Savio Sengupta, Manash Chanda, Swarnil.Roy, “Analytical Modeling of D.C Parameters of Double Gate Junctionless MOSFET in Near & Subthreshold Regime for RF Circuit Application”, Nanoscience and Nanotechnology–Asia, Bentham Science, July-2019. ( DOI: 10.2174/2210681209666190730170031).
Savio Jay Sengupta, Dipanjan Sen, Swarnil Roy, Manash Chanda, and Subir Kumar Sarkar, “D.C. Performance Analysis of High-K Adiabatic Logic Circuits in Sub-Threshold Regime for RF Applications”, Sensor Letter, American Scientific Publisher, vol. 17, pp. 487–496 (2019).
D.Sen, S.J .Sengupta, S.Roy, M.Chanda, S.K.Sarkar " D.C Performance Analysis of Sub-Threshold Source-Coupled Logic Circuit Using Double Gate Junction-Less MOSFET for Low-Power Application" Sensor Letter, American Scientific Publisher, 17, no. 7, pp. 538– 545, 2019.
2018:
Rahul Das, Manash Chanda, Chandan K Sarkar,“Analytical modeling of charge plasma based optimized nanogap embedded surrounding gate MOSFET for label free biosensing”,IEEE Transaction on Electron Device,vol. 65, issue 12, pp. 5487-5493, Oct 2018.( DOI: 10.1109/TED.2018.2872466).
Manash Chanda, Sandipta Mal, Akash Mondal, Chandan Kumar Sarkar "Design and Analysis of a Logic Model for Ultra Low Power Near Threshold Adiabatic Computing", IET Circuits Devices & Systems, vol. 12, issue 4, pp. 439-446, February 2018. (DOI: 10.1049/iet-cds.2017.0347).
2017:
Manash Chanda, Rahul Das, Atanu Kundu, Chandan Kr. Sarkar " Analytical Modeling of Label Free Biosensor Using Charge Plasma Based Gate Underlap Dielectric Modulated MOSFET ", Superlattices and Microstructures(Elsevier), vol. 104, pp. 451-460, April 2017.Impact Factor : 2.117. (DOI: http://doi.org/10.1016/j.spmi.2017.03.010)ISSN: 0749-6036.
Manash Chanda, Tanushree Ganguli, Sandipta Mal, C.K.Sarkar "Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application", DOI: 10.1166/jolpe.2017.1505, Journal of Low Power Electronics, American Scientific Publishers, Vol. 13, issue 3, pp. 472-481,September, 2017.
Aatrayee Das, Prachi Agarwal, Subhra Sarkar, Sudeshna Mukherjee, Manash Chanda, Swapnadip De " Modelling of Surface Potential and Drain Current for linearly doped short channel nMOSFET with Inner Fringing Field”, Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print);EISSN: 2222-7067 (Online), vol. 5, issue 1, pp. 1-6.
Sudeshna Mukherjee, Subhra Sarkar, Prachi Agarwal, Aatrayee Das, Manash Chanda, Swapnadip De"Modelling of the basic parameters for Gaussian doped Symmetric Double Halo Dual Material Gate n-MOSFET ”, Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print); EISSN: 2222-7067 (Online), vol. 5, issue 1, pp. 7-11.
Manash Chanda, Tanushree Ganguli, Rounak Dutta, Shouvik Mukhopadhyay, Swapnadip De "Design and Implementation of 8T Full Adder for High Speed Application”, Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print); EISSN: 2222-7067 (Online), vol. 5, issue 1.
Manash Chanda, Tanushree Ganguli, Rounak Dutta, Shouvik Mukhopadhyay, Swapnadip De, "Design and Implementation of 8x8 Adiabatic Multiplier using Single Phase AdiabaticDynamic Logic”, Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print);EISSN: 2222-7067 (Online), vol. 5, issue 1.
2016:
Gargi Jana, Dipanjan Sen and Manash Chanda, “ Junctionless double gate non-parabolic variable barrier height Si-MOSFET for energy efficient application”, Journal of Microsystem Technologies, Springer, pp. Nov, 2019, . [SCI, Impact factor: 1.6], (DOI: 10.1007/s00542-019-04688-6).
Manash Chanda, Ananda Sankar Chakrabarty, Chandan Kumar Sarkar ” Complete delay modeling of sub-threshold CMOS logic gates for low-power application”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (Wiley onlineLibrary),vol. 29, issue 2, pp. 132-145, March 2016. (DOI: 10.1002/jnm.2053).
2015:
Manash Chanda, Sankalp Jain, Swapnadip De, C.K.Sarkar “Implementation of Sub-threshold Adiabatic Logic (SAL) for ultra Low Power Application”, IEEE Transactions on Very Large Scale Integration Systems, vol. 23, issue 12, pp. 2782-2790, Jan. 2015. (DOI:10.1109/TVLSI.2014.2385817).
Manash Chanda, Prithu Dey, Swapnadip De, C.K.Sarkar "Novel Charge Plasma Based Dielectric Modulated Impact Ionization MOSFET as a Biosensor for Label-Free Detection", Superlattices and Microstructures (Elsevier), vol. 86, pp. 446-455, August 2015. (http://dx.doi.org/10.1016/j.spmi.2015.08.013).
Manash Chanda, Swapnadip De, C.K.Sarkar ” Design and Analysis of 32 Bit CLA Using Energy Efficient Adiabatic Logic for Ultra Low Power Application”, Journals of Circuits, systems and computers (World Scientific), vol. 24, issue 10, Dec. 2015. (DOI:http://dx.doi.org/10.1142/S0218126615501601).
2014:
Manash Chanda, Swapnadip De, Chandan Kumar Sarkar “Modeling of Characteristic Parameters for Nano-scale junctionless Double Gate MOSFET considering Quantum Mechanical Effect”, Journal of Computational Electronics (Springer), vol. 14, issue 1, pp. 262-269, December 4, 2014. ( DOI: 10.1007/s10825-014-0648-y).
Debarati Das, Swapnadip De, Manash Chanda, C K Sarkar "Modelling of sub-threshold surface potential for short channel Double gate Dual Material Double Halo MOSFET" , The IUP Journal of Electrical & Electronics Engineering, ICFAI University Press, vol.7 issue no.4, pp. 19-42, October 2014
2013:
Manash Chanda, Swapnadip De, C.K.Sarkar “Modeling of Parameters for Nano-Scale Surrounding Gate nMOSFET considering Quantum Mechanical Effects”, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (Wiley Online Library), vol. 27,issue 5-6, pp. 883-895, Dec 2013. (DOI: 10.1002/jnm.1965).
List of Books / Books Chapter Publications :
Amit Bhattacharyya, Manash Chanda and Debashis De , Published Book chapter in “Emerging Trends in Terahertz Solid-State Physics and Devices”, Springer, pp 107-120, March 2020 .
Amit Bhattacharyya, Manash Chanda and Debashis De, "Dielectrically Modulated Bio-FET for Label-Free Detection of Bio-molecules " Published Book chapter in Modern Techniques in Biosensors, pp. 183-198 , 2021.
M. Chanda, "Design of Microcontroller Based Embedded Water Level Sensor" (ISBN 978-3- 8473-0681-8) Publisher: Lambert Academic Publishing, a trademark of: Omni Scriptum GmbH & Co. KG, Heinrich- Böcking-Str. 6-8,66121, German, www.lap-publishing.com.
M. Chanda, A. S. Chakrabarty, “Reversible Logic Based Ultra Low Power Arithmetic Logic Circuit Design", ISBN 978-3-659-53914-5,Publisher: Lambert Academic Publishing, a trademark of: Omni Scriptum GmbH & Co. KG, Heinrich- Böcking-Str. 6-8,66121, Saarbrücken, German, www.lap-publishing.com.
Swapnadip De, Manash Chanda, Chandan Kumar Sarkar “Channel And Gate Engineered Double Gate MOSFET" (ISBN 978-3-659-56479-6). Publisher: Lambert Academic Publishing, a trademark of: Omni Scriptum H & Co. KG, Heinrich- Böcking-Str. 6-8,66121, German, www.lap-publishing.com.
A Sarkar, Swapnadip De, Manash Chanda, C. K. Sarkar “Low Power VLSI Design”, Publisher: DE GRUYTER, Genthiner Str. 13. 10785 Berlin, Germany,ISBN:9783110455267, www.degruyter.com, published in 2016.
Bhattacharyya A.;Chanda M.;De D, "Dielectrically Modulated Bio-FET for Label-Free Detection of Bio-molecules", Studies in Systems, Decision and Control, Volume 327, Year 2021, Pages 183-198.
Swarnil Roy, Manash Chanda, Liquid Crystal Switches, Optical Switching: Device Technology and Applications in Networks , https://doi.org/10.1002/9781119819264.ch8 .
Sudipta Ghosh,Chandan Kumar Sarkar, Manash Chanda, "Acousto-Optic Switches", Optical Switching: Device Technology and Applications in Networks , First published: 08 July 2022 https://doi.org/10.1002/9781119819264.ch5
Bhattacharyya, A., Paul, S., Debnath, P., De, D., Chanda, M. (2023). Performance Assessment of Electrostatically Doped Dual Pocket Vertical Tunnel Field-Effect Transistor. In: Lenka, T.R., Misra, D., Fu, L. (eds) Micro and Nanoelectronics Devices, Circuits and Systems. Lecture Notes in Electrical Engineering, vol 904. Springer, Singapore. https://doi.org/10.1007/978-981-19-2308-1_24
Arighna Basak, Writam Banerjee, Avtar Singh, Avik Chakraborty, Manash Chanda, Chapter 12 - Emerging non-CMOS devices and technologies, In Micro and Nano Technologies,Nanoelectronics : Physics, Matrials and Devices, Elsevier,2023,Pages 263-303,ISBN 9780323918329, https://doi.org/10.1016/B978-0-323-91832-9.00014-2.
Richa Gupta, Arighna Basak, Rakesh Vaid, Papiya Debnath, Manash Chanda, Hafizur Rahman, "Chapter 14 - Application of nanoscale devices in circuits," In Micro and Nano Technologies, Nanoelectronics : Physics, Materials and Devices, Elsevier, 2023, Pages 359-384, ISBN 9780323918329, https://doi.org/10.1016/B978-0-323-91832-9.00017-8.
Differential Equation Based Solutions for Emerging Real-Time Problems, Edited By Papiya Debnath, Biswajit Sarkar, Manash Chanda, October 30, 2023 by CRC Press, ISBN 9781032131382
Suman Lata Tripathi; Deepika Ghai; Sobhit Saxena; Manash Chanda; Mamoun Alazab, "Machine Learning Algorithms for Signal and Image Processing", IEEE Eiley Press, 2023, https://ieeexplore.ieee.org/servlet/opac?bknumber=9960833
List of Conference Publications:
M. Chanda, A. Dandapat and H. Rahaman, “Low power sequential circuit by using Single Phase Adiabatic Dynamic Logic,” 2009 International Conference on Computers and Devices for Communication, CODEC-2009, Kolkata, pp. 1-4. (included in IEEE XPLORE)
M. Chanda, R. Mitra, P. Sil, A. Dandapat and H. Rahaman, “Comparative analysis of Adiabatic compressor circuits for ultra low power DSP application ,” Advances in Recent technologies in Communication and Computing, ARTCOM 2010 , Kerala, pp. 355-59. (included in IEEE XPLORE)
M. Chanda, S. Naha, S. Manna, A. Dandapat and H. Rahaman, “Implementation of ultra low power 8 bit CLA using Single phase adiabatic dynamic logic,” Advances in Recent technologies in Communication and Computing, ARTCOM 2010, Kerala, pp. 360-64. (included in IEEE XPLORE)
M. Chanda, S. Kundu, I. Adak, A. Dandapat and H. Rahaman, “Design and Analysis of Tree-Multiplier using Single-Clocked Energy Efficient Adiabatic Logic,” TECHSYM 2011, IEEE students section, Kharagpur IIT (included in IEEE XPLORE) .
M. Chanda, S. Banerjee, D. Saha, S. Jain, “Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier”, IMAC4s, pp. 801-806., 2013. (included in IEEE XPLORE)
Chakraborty, A.S. ; Chanda, M. ; Sarkar, C.K. “Analysis of noise margin of CMOS inverter in sub-threshold regime”, SCES, pp. 1-5, 2013. (included in IEEE XPLORE)
Jain S.,Chanda, M., Sarkar, C.K. “Comparative analysis of delay for sub-threshold CMOS logics”, SCES, 2013. (included in IEEE XPLORE)
M. Chanda, A. S. Chakraborty, S. Nag, R. Modak, “Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application”, IEEE VDAT-2014, pp. 1-2, 2014. (Included in IEEE Xplore).
Manash Chanda, Jeet Basak, Diptansu Sinha, Tanushree Ganguli and Chandan K.Sarkar,”Design and Implementation of Adiabatic Multiplier in Sub-threshold regime forUltra low Power Application”, IEEE- ICCSP 2016, (Included in IEEE Xplore).
Manash Chanda, Diptansu Sinha, Jeet Basak, Tanushree Ganguli and Chandan K. Sarkar,”Design and Analysis of Adiabatic Complex Sequential logic circuits in Sub-thresholdregime for Ultra-low power application”, IEEE- ICCSP 2016, (Included in IEEE Xplore).
Manash Chanda, Rounak Dutta, Aliyasmin Rahaman and Chandan Kumar Sarkar, “Analysis of NAND/NOR Gates using Subthreshold Adiabatic Logic (SAL) for Ultra Low Power Applications”, IEEE MICROCOM 2016, (Included in IEEE Xplore).
Manash Chanda, Prithu Dey, Angsuman Sarkar, Chandan Kumar Sarkar, “Doping-lessdouble gate impact ionization MOSFET for high switching application,” IEEE ICDCS, pp. 179-183, 2016. (Included in IEEE Xplore)
Manash Chanda, Diptansu Sinha, Jeet Basak, Tanushree Ganguli and Chandan Sarkar, “Design and Analysis of Adiabatic Logic in Sub-threshold Regime for Ultra Low Power Application”, IEEE ICEDSS 2016, included in IEEEExplorer.( Best Paper Award).
Manash Chanda, Jeet Basak, Diptansu Sinha, Tanushree Ganguli and Chandan Sarkar, “Comparative Analysis of Adiabatic Logics in Subthreshold Regime for Ultra-Low Power application”, IEEE ICEDSS 2016, included in IEEEExplorer. (Best Paper Award).
Sandipta Mal, Anindita Podder, Anirban Chowdhury, Manash Chanda, "Comparative Analysis of Ultra Low Power Adiabatic Logics in Near-Threshold Regime", presented in 2nd International Conference IEEE-DevIC 2017, March 23-24, 2017, Kalyani Government Engineering College, Kalyani. (included in IEEE Xplore).
Anindita Podder, Sandipta Mal, Anirban Chowdhury, Akash Mondal, Manash Chanda, "Design and Analysis of Adiabatic Adder in Near-Threshold Regime for Low Power Application", presented in 2nd International Conference IEEE-DevIC 2017, March 23-24, 2017, Kalyani Government Engineering College, Kalyani. (included in IEEEXplore).
Akash Mondal, Sandipta Mal, Anirban Chowdhury, Anindita Podder,Manash Chanda "Analysis of Adiabatic NAND/NOR for Ultra-Low Power Near Threshold Computing", presented in 2nd International Conference IEEE-DevIC 2017, March 23- 24, 2017, Kalyani Government Engineering College, Kalyani. (included in IEEE Xplore)
Anirban Chowdhury, Sandipta Mal, Shruti Goswami, Akash Mondal, Swapnadip De, Manash Chanda "Adiabatic Implementation of Reversible Architecture”, presented in 2nd International Conference IEEE-DevIC 2017, March 23-24, 2017, Kalyani Government Engineering College, Kalyani. (included in IEEE Xplore)
ShrutiGoswami, Budhaditya Chowdhury, Manash Chanda, " Analytical Modelling of Power dissipation and Voltage swing of CMOS logic circuit for Near-Threshold Computing”, presented in2nd International Conference IEEE-DevIC 2017, March 23-24, 2017, Kalyani Government Engineering College, Kalyani. (included in IEEE Xplore)
Soumen Pal, Manash Chanda, " Design and analysis of large unity gain bandwidth operational amplifier for low-voltage applications”, presented in 2nd International Conference IEEE-CALCON,Dec 2-3 Dec, 2017. (included in IEEE Xplore).
Gargi Jana, Madhuchhanda Majumdar Manash Chanda, Chandan K. Sarkar4, “Analysis of Gate misalignment Effects in Double Gate Junctionless MOSFET”, accepted in IEEE ICACCT 2018, pp. 122-125, India, (included in IEEE Xplore).
Savio Jay Sengupta, Samarthi Chakraborty, Tamal Sarkar, Md. Zishan Iqbal and Manas Chanda,”Effect of High -K Dielectric on the Performances of Adiabatic Logic Circuits in Sub -threshold Regime”, Accepted in IEEE EDKCON 2018,included in IEEE Explore.
Gargi Jana and Manash Chanda, “Analytical Modeling of Drain Current of Junctionless Double Gate Si - MOSFET having Variable BarrierHeight Considering Band Non -Parabolicity”, Accepted in IEEE EDKCON 2018, included in IEEE Explore.
Ruben Ray, Sagnik Ghoshal and Manash Chanda, “Small Signal Modeling of Cylindrical/Surrounding Gate MOSFET for RF Application Incorporating Fringing Effect”,Accepted in IEEE EDKCON 2018, included in IEEE Explore.
Mainak Mukherjee, Manash Chanda, Anup Dey and Angsuman Sarkar,”Effect of Band Parabolicity on Energy Sub -Band Profile for Nano - Dimensional Junctionless Metal Oxide Semiconductor Field Effect Transistors” Accepted in IEEE EDKCON 2018, included in IEEE Explore.
M. Sen, A. Gatait, S. Ghosh, M. Chanda and A. Sarkar, “Verilog-A Modeling of Junction-less MOSFET in Sub- Threshold Regime for Ultra Low-Power Application”, IEEE WITCON ECE 2019, will be included in IEEE.
M. Chanda, S. De, A. Ghosh, D. Banerjee, P. Biswas “A Novel Design Of Low Power Low Voltage Full Adder Using 14 MOSFETS. ”International conferences on modeling and simulations, Kolkata, Dec 3-5, 2007.
M. Chanda and P. Mukherjee, “An ECRL based energy efficient pseudo random sequence generator for direct sequence spread spectrum system,” NCART, pp. 27-32, 30th Jan-1st Feb, 2009.
M. Chanda, D. Das and A. Dandapat, “Design of area- efficient high-speed low- ower single bit adder cell,” CCCIT, kolkata, pp. 645-651,6th-7th, Feb 2009.
Manash Chanda, Swapnadip De “Design and Implementation of Ultra Low-Power 8x8 Adiabatic Multiplier using SPADL", Proceedings of DRDO and CSIR sponsored 2nd National Conference on Advanced Communication Systems and Design Techniques (NCACD2012),vol.1,pp.29-30 September 2012, Haldia Institute of Technology, India.
Dr.Swapnadip De, Dr.Angsuman Sarkar, Manash Chanda and Dr. Chandan Kumar Sarkar "Study of Surface Potential and Threshold Voltage for non-uniformly doped DHDMG n-Mosfet", 4th International Conference on Technical and Managerial Innovation in Computing and Communications in Industry and Academia (IEMCON 2013), pp.56-60, August 23, 2013, Kolkata.
Manash Chanda, Prithu Dey, Swapnadip De, C K Sarkar "Modelling of RF Parameters for Nano-scale junctionless Double Gate MOSFET considering Fringing Effect", Proceedings of 3rd International Conference on Nanotechnology (NANOCON 2014), October 14-15, 2014, Pune, India, organized by Bharati Vidyapeeth University in association with North Carolina State University, The University of Tokushima, Tuskegee University and MET.
Manash Chanda, Indu Gopal Maity, Sabyasachi Chandra, T Ganguli, Swapnadip De, C KSarkar "Implementation of 8 bit CLA using Single Clock Powered Energy-Efficient Adiabatic Logic" CCSN 2015, December 24-25, 2015, Kolkata.
Sandipta Mal, Swapnadip De, Manash Chanda et. al., "Design and Analysis of Nano-dimensional Full Adder in Near Threshold Regime for Low Power Application".Proceedings of IEEE EDS Kolkata Chapter Technically cosponsored 1st International Conference NANOBIOCON 2016 on October 3-5, 2016 at Science City, Kolkata, abstract in pp. 101.
Sandipta Mal, Anindita Poddar, Akash Mondal, Manash Chanda, Dr.Swapnadip De, "Design and Implementation of Low Power 7-segment Decoder in Near-Threshold Regime", Proceedings of Micro 2016 (Junior), 3rd International Conference Micro 2016 organized by MAKAUT, in association with IASTM, IEEE EDS Kolkata Chapter, July 9-10, 2016, Science City, Kolkata, pp. 1-3.
Swapnadip De, M.Chanda,A.Sarkar “Analytical Sub-threshold Surface Potential and Drain Current Model for Linearly Doped Double Halo DMG MOSFET", Proceedings of DRDO and CSIR sponsored 2nd National Conference on Advanced Communication Systems and Design Techniques (NCACD 2012),vol.1,pp.67-70,29-30 September2012,Haldia Institute of Technology,India.
M. Chanda, Swapnadip De “Design and Implementation of Ultra Low-Power 8x8 Adiabatic Multiplier using SPADL", Proceedings of DRDO and CSIR sponsored 2nd National Conference on Advanced Communication Systems and Design Techniques (NCACD2012),vol.1, pp.29-30 September2012,Haldia Institute of Technology,India.
Swapnadip De, Angsuman Sarkar, Manash Chanda and Dr.Chandan Kumar Sarkar "Study of Surface Potential and Threshold Voltage for non-uniformly doped DHDMG n-Mosfet",Proceedings of IEEE EDS Kolkata Chapter sponsored 4th International Conference on Technical and Managerial Innovation in Computing and Communications in Industry and Academia (IEMCON 2013), pp.56-60, August 23,2013, Eagle Eye Publications, India, organized by IEM, Kolkata.
Sandipta Mal, Anindita Poddar, Akash Mondal, Manash Chanda, Dr. Swapnadip De, "Design and Implementation of Low Power 7-segment Decoder in Near-Threshold Regime", Proceedings of Micro 2016 (Junior), 3rd International Conference Micro 2016 organized by MAKAUT, in association with IASTM, IEEE EDS Kolkata Chapter, July 9-10, 2016, Science City, Kolkata, pp. 1-3.
Amit Bhattacharyya; Prithviraj Pachal; Anirban Pradhan; Manash Chanda; Debashis De, “Performance Analysis of Underlap Double Gate Oxide Stacked Junctionless MOSFET for Analog and RF Applications”, IEEE 2019 International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks (IMICPW), 22-24 May 2019, DOI: 10.1109/IMICPW.2019.8933249.
Amit Bhattacharyya;Adrija Mukherjee; Manash Chanda; Debashis De, “Advantages of Charge Plasma Based Double Gate Junctionless MOSFET Over Bulk MOSFET for Label Free Biosensing”, IEEE 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 18-19 July 2020, Kolkata, India.
Adrija Mukherjee; Baishali Ray; Debankan Das; Shaon Bhattacharyya; Papiya Debnath and Manash Chanda, “Impact of Temperature on Circuit Performances of Junctionless MOSFET in Sub-threshold Regime”, IEEE 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 18-19 July 2020, Kolkata, India.
Hemanga Banerjee;Kinjol Sarkar;Papiya Debnath;Swarnil Roy and Manash Chanda “Design and Analysis of Double Gate Tunnel Field Effect Transistor using Charged Plasma: IEEE 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS), 18-19 July 2020, Kolkata, India.
S. Majumder, S. Bhattacharyya, P. Debnath and M. Chanda, "Power Delay Analysis of CMOS Reversible Gates for Low Power Application," 2020 International Conference on Computational Performance Evaluation (ComPE), 2020, pp. 620-625, doi: 10.1109/ComPE49325.2020.9200136. .
S. Sarkar, P. Debnath, M. Chanda and D. De, "DFT Based approach to sense SF6 decomposed gases (SO2, SOF2, SO2F2) using Ni doped WS2 monolayer," IEEE 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 643-647, doi: 10.1109/DevIC50843.2021.9455892.
G. Jana, P. Debnath and M. Chanda, "A Dielectric Modulated MOS transistor for Biosensing," IEEE 2021 Devices for Integrated Circuit (DevIC), 2021, pp. 484-488, doi: 10.1109/DevIC50843.2021.9455935.
Amit Bhattacharyya, Shaonli Paul, Papiya Debnath, Debashis De, Manash Chanda, "Performance Assessment of Electroscatically Doped Dual Pocket Vertical Tunnel Field EffecEffect TranTransistor "2nd Int. conference on Micro/Nanoelectronics Devices, circuits and Systems (MNDCS-2022) (29-31 JAN 2022).
Patents :
Patent Application Number-346552-001
C.B.R Number-205452; CBR date: 22/07/2021
Title: IoT BASED COST EFFECTIVE OXYGEN CONCENTRATOR under Intellectual Property Right, Govt of India.
Status: Published; Publication Date: 06/05/2022
Inventors: Dr. Papiya Debnath, Dr. Manash Chanda, Subhrapratim Nath, Indrajit Das, Dr. Renuka Sharma, Vipluv Pathak, Dr. Shikha Saxena, Meghna Garg
https://drive.google.com/file/d/1oxiiFANlu9Edims0nWjw2e2HzhSVd49m/view?usp=share_link
2. Patent Application Number-350721-001
C.B.R Number-208339; CBR date: 05/10/2021; Status: Published; Publication Date: 16/12/2022
Title: IOT BASED GAS CHROMATOGRAPHY under Intellectual Property Right, Govt of India.
Inventors: Prof. Subhrapratim Nath, Dr. Manash Chanda, Dr. Papiya Debnath, Prof. Indrajit Das, Dr. Swapnadip Dey, Prof. Sudipto Ghosh, Dr. Anup Dey, Prof. Aishwarya Dhara
https://search.ipindia.gov.in/DesignApplicationStatus
https://drive.google.com/file/d/1XEuMXS6a1J-V-vJY16J3dJ2bf5WLna5R/view?usp=share_link
3. Application Number: 202211069583
Application Type: Ordinary Application; Date of Filing: 02/12/2022
Applicant Name: Dr. Amit Khare; Mohamed J. Saadh; Mr. Sivakumar S.; Dr. Papiya Debnath; Dr. Manash Chanda; Dr. Sheshang Degadwala
Title of Invention: AI AND MACHINE LEARNING BASED EARLY DETECTION, PREDICTION AND CLASSIFICATION OF BRAIN TUMORS AND SEGMENTATION OF ITS STAGES USING IMAGE PROCESSING TECHNIQUES
Field of Invention: Computer Science
Status: Published
Publication Date (U/S 11a): 09/12/2022
https://drive.google.com/file/d/1CoyDFS5AN_xQa5UtHoPI-D1A9TMrMuT1/view?usp=share_link
4. Application Number: 202331013263
Application Type: Ordinary Application; Date Of Filing: 27/02/2023
Applicant Name: Dr. Manash Chanda, Dr. Papiya Debnath, Prof. Indrajit Das, Prof. Subhrapratim Nath, Dr. Swapnadip De, Prof. Sudipta Ghosh
Title Of Invention: A Intelligent Machine Learning Based Healthcare System For Medical Emergency
Field Of Invention: Computer Science ; Status: Published
PUBLICATION DATE (U/S 11A) 10/03/2023
https://drive.google.com/file/d/1WEO0b-9-EB93f6fnxIFXSelm_oiWaHv-/view?usp=share_link
5. Application Number: 202331057524
Application Type: Ordinary Application; Date Of Filing: 28/08/2023
Applicant Name: Dr. Manash Chanda, Prof. Indrajit Das, Dr. Papiya Debnath, Dr. Swapnadip De, Prof. Sudipta Ghosh, Dr. Swarnil Roy, Prof. Subhrapratim Nath, Prof. Papiya Das, Prof. Joyanto Roychoudhary
Title Of Invention: Artificial Intelligence Based System For Prediction And Prevention Of Kidney Disease Using Machine Learning Algorithms
Field Of Invention: Computer Science; Status: Published; Publication Date (U/S 11a) 24/11/2023
https://drive.google.com/file/d/1_AKawVrALF7jKMGjBVs7dQMZVkblsQk_/view?usp=drive_link
Reviewer of International Journals/Conferences:
Reviewer of the following International Journals/Conferences:
Transaction on VLSI, Transaction on Circuit and System, Regular paper I and II (IEEE)
Transaction on Electron Device (IEEE)
Solid state Circuits, Superlattice and Microstructure, Microelectronics Engineering (ELSEVIER)
Journal of Computational Electronics. (SPRINGER)
International Journal of Electronics, Taylor and Francis, UK.
IET Circuit, Device and System (IET, UK).
Int. Journal of Numerical Modelling: Electronic Networks, Devices and Fields, (John Wiley & Sons Inc.)
World Scientific and Engineering Academy and Society (WSEAS Transactions/Conferences), Athens, Greece.
Journal of Low power Electronics, (American Scientific Publisher)
Students Guidance:
Ph. D Guidance:
AMIT BHATTACHARYA, ASSISTANT PROFESSOR, DEPT. OF ECE, HALDIA INST. OF TECHNOLOGY
Thesis Title: Design and Analysis of Dielectrically Modulated Bio- FET for Label Free Detection of Bio-molecules
Date of Enrollment: 5.10.2020
University: Maulana Abul Kalam Azad Institute of Technology, West Bengal, India
Status: Ongoing
SUMAN SARKAR, ASSISTANT PROFESSOR, DEPT. OF ECE, UNIVERSITY OF ENGINEERING AND MANAGEMENT
Thesis Title: Molecular Modelling of Nanostructure For Sensing
Date of Enrollment: 5.10.2020
University: Maulana Abul Kalam Azad Institute of Technology, West Bengal, India
Status: Ongoing
MAINAK MUKHERJEE, PRINCIPAL, POLYTECHNIC CLG-TIG
Thesis Title: Modelling Of Emerging MOSFET Structures For Circuit Analysis
Date of Enrollment: 9.10.2020
University: Maulana Abul Kalam Azad Institute of Technology, West Bengal, India
Status: Ongoing
Internship:
Ms. Ananya Karmakar, M. Sc., Calcutta University
Projects Ongoing/Completed
Title: Design and Optimization of Simulated Tubular Tunnel FET Structures for Biosensing Applications
Team Members
Dr. Dereje Tekilu Principal Investigator
Dr. Avtar Singh Principal Investigator
Dr. Gangiregula Subbarao Co- Investigator
Dr. Manash Chanda Co- Investigator
Funded by: Adama Science and Technology University
Amount: 197,324 BIRR
Title: Design and Optimization of Simulated Tubular Tunnel FET Structures for Biosensing Applications
Team Members
Dr. Dereje Tekilu Principal Investigator
Dr. Avtar Singh Principal Investigator
Dr. Gangiregula Subbarao Co- Investigator
Dr. Manash Chanda Co- Investigator
Funded by: Adama Science and Technology University
Amount: 197,324 BIRR
Title: Design and Optimization of Simulated Tubular Tunnel FET Structures for Biosensing Applications
Team Members
Dr. Dereje Tekilu Principal Investigator
Dr. Avtar Singh Principal Investigator
Dr. Gangiregula Subbarao Co- Investigator
Dr. Manash Chanda Co- Investigator
Funded by: Adama Science and Technology University
Amount: 197,324 BIRR