Chiplets have become a compelling approach to scaling and heterogeneous integration of workload-specific processors and massive bandwidth memory systems into computing systems. Examples include integrating die from multiple function-optimized process nodes into one SoC, or integrating silicon from multiple businesses into one SoC.

Chiplet-based products have been produced in high volume by multiple companies using proprietary chiplet ecosystems. Recently, the community has proposed several new standards (e.g., UCIe, BoW, etc.) to facilitate integration and interoperability of any compliant chiplet. Hyperscalers (e.g., Google, Amazon) are actively designing high volume products with chiplets through these open interfaces. Other communities are exploring the end-to-end workflow and tooling to assemble chiplet-based SoCs. High performance computing can benefit from this trend. However, the performance, power, and thermal requirements unique to HPC, present many challenges to realizing a vision for affordable, modular HPC using this new approach. 

This workshop, organized jointly by DOE labs and the Open Compute Project (OCP), will bring together a diverse group of experts to discuss the benefits and challenges of the codesign, manufacturing, and deployment of future chiplet-based architectures. Expected benefits include better reuse of IP, easier customization, improved performance for specific HPC workloads, more flexibility, and heterogeneous integration of various types of semiconductor dies into a package. The challenges include more complex packaging, emerging electrical and mechanical standards, software, and more complex supply chains.  The discussion will also bring in industry and market experts to evaluate the likelihood that an open  chiplet economy will be available for system developers to investigate, prototype, design, and use chiplet architectures.  Chiplets could be multicore processors, GPUs, FPGAs, networking interfaces, optical engines, memory controllers, or any number of specialized accelerators. 

To a first order, the topics to be covered are

• An introduction to chiplets (to level-set attendees from multiple orgs);

• An overview of the potential evolution of system architectures with chiplets

  • • recent commercial developments, including startups and consortia, with a focus on highlighting the heterogeneity and scaling made possible with chiplets

    • the benefits and challenges offered by heterogeneous integration – cost management, specializing functions to process nodes for analog and optical components,

• A deeper dive into

  • • DoE-relevant uses for chiplets in HPC and high-performance sensors, with a focus on leveraging commercial developments from leading vendors and start ups;-

    • Chiplet uses cases for other government agencies including NASA, DARPA, AFRL and the Intelligence community. As an opportunity to highlight the potential benefits of heterogeneity in meeting unique requirements such as rad-hard, ultra-low-power or other extreme environments.

• Brainstorming sessions for

  • • research opportunities and Priority Research Directions (PRDs) related to chiplets

    • opportunities to accelerate the open chiplet economy. A deeper dive into identifying and enabling where open source projects in silicon, EDA, tooling and software can benefit the open chiplet economy.

The goal of the workshop is to share the latest developments in the chiplets ecosystem, outline the benefits and challenges of an open chiplet economy identify basic research challenges with this architectural strategy and catalyze work in this area in academia, government labs and industry. It is critical that we identify potential collaborations with system vendors including hyperscalers, electronic design automation (EDA) vendors, device manufacturers, and standards organizations. The workshop participants will produce a collaboratively-authored white paper on chiplets for HPC within a six months after the workshop.

Why Now?

Chiplet-based HPC systems are now becoming mainstream with companies such as AMD and Intel using chiplet architectures for their respective Exascale computing systems and across their product offerings. The national semiconductor strategy as outlined in the CHIPS act also envisions a role for chiplets in onshoring manufacturing. The technology allows us to further progress Moore’s Law and provide higher levels of integration in the systems being deployed.  As vendors like AMD open their designs to 3rd party chiplets, and even use open chiplet die-to-die communication standards like BoW and UCIe, it could create a rich environment for realizing specialized computing systems for targeted workloads.  There is enormous interest in understanding the opportunities and limitations of chiplet technology as well as the economic model for sustaining their ecosystem.

Organization

We will create a program committee consisting of representation from across the DOE laboratory complex, academics, and industry participants who are deeply engaged in the burgeoning chiplet ecosystem. The program committee will help us to organize the content and invitations for the workshop (slated for August 2023), which will focus on level-setting the HPC community on the current state of the art in Chiplets technology and ecosystem.  This might be followed up by an additional workshop or even an event associated with the forthcoming “Chiplets Summit” that will solicit whitepapers from the community that will envision potential research in Chiplets with impacts and outcomes. We will advertise the workshop across the DOE national laboratory complex and invite participants based on submitted abstracts.