A fast mixed-signal simulation framework for RRAM-based CIM NPUs that integrates event-driven analog CIM modeling with RTL digital subsystems and RISC-V firmware execution for practical NPU-level verification. 

A modular block-reuse processor for configurable-size complex QR decomposition and QRD-based matrix inversion that supports 4×4 to 16×16 matrices by reusing fixed 4×4 arithmetic cores with CORDIC-based systolic processing. 

A hardware-efficient CDR-less ADC-DSP receiver that achieves infinite-range timing recovery under frequency offset by switching odd/even FSE input windows within a single FIR datapath. 

A scalable MIMO detector architecture for massive MIMO systems that combines distributed ADMM processing, deep-unfolded penalty optimization, and hardware-efficient Richardson iteration to improve detection performance with predictable resource scaling. 

Neural Network-Based Symbol Detection directly estimates transmitted symbols from received signals using a neural network. Instead of explicitly relying on a channel model or channel state information (CSI), the network learns the relationship between received samples and transmitted symbols from training data. This allows the detector to jointly compensate for inter-symbol interference (ISI), noise, and nonlinear distortion, making it effective for complex or long-memory communication channels.