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Research Area
Research Area
High-Speed Link Circuits and Systems
6G Digital Processor for Massive-MIMO
In-Memory Computing Macro / ML Hardware Accelerator
Automation Methodologies for Analog/Mixed-Signal (AMS) Circuits
Research Goal: Developing Integrated AI Hardware Solutions Spanning from Data Center to Edge
Fast Mixed-Signal Simulator for RRAM-Based CIM NPUs
Fast Mixed-Signal Simulator for RRAM-Based CIM NPUs
A fast mixed-signal simulation framework for RRAM-based CIM NPUs that integrates event-driven analog CIM modeling with RTL digital subsystems and RISC-V firmware execution for practical NPU-level verification.
Configurable Complex QR Decomposition and Matrix Inversion Processor
Configurable Complex QR Decomposition and Matrix Inversion Processor
A modular block-reuse processor for configurable-size complex QR decomposition and QRD-based matrix inversion that supports 4×4 to 16×16 matrices by reusing fixed 4×4 arithmetic cores with CORDIC-based systolic processing.
Single-Datapath Switched FSE Receiver for CDR-Less Timing Recovery
Single-Datapath Switched FSE Receiver for CDR-Less Timing Recovery
A hardware-efficient CDR-less ADC-DSP receiver that achieves infinite-range timing recovery under frequency offset by switching odd/even FSE input windows within a single FIR datapath.
Scalable Distributed ADMM MIMO Detector with Deep-Unfolded Penalty Parameters
Scalable Distributed ADMM MIMO Detector with Deep-Unfolded Penalty Parameters
A scalable MIMO detector architecture for massive MIMO systems that combines distributed ADMM processing, deep-unfolded penalty optimization, and hardware-efficient Richardson iteration to improve detection performance with predictable resource scaling.
OFDM-Based Adaptive Bit-Loading RX Design for High-Speed Wireline Links
OFDM-Based Adaptive Bit-Loading RX Design for High-Speed Wireline Links
An OFDM-based Per-QAM adaptive bit-loading receiver design for high-speed wireline links that dynamically assigns QAM orders based on subcarrier SNR and applies LUT-based BER approximation to reduce hardware complexity while satisfying the target BER with improved area and power efficiency.
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