For a complete lists of publications, please see Google Scholar
International Technical Papers
* denotes corresponding author
2025
##, S.Ryu*, "----" (Under Review)
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S. Konno, C-K. Liu, S. Ryu, S. Speltalnick, A Raychowdhury, "A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro using 2D-Weighted Capacitor Array for Complex Number MAC Operations"
IEEE Asian Solid-State Circuits Conference (ASSCC)
S. Konno, Z. Ellis, A. Golder, S. Ryu, D. Dinu, A. Varna, S. Mathew, A. Raychowdhury, "A 65nm Delta-Sigma ADC based VDD-Variation-Tolerant Power-Side-Channel-Attack Sensor"
IEEE Solid-State Circuits Letters (SSC-L)
2024
A. Assoa, A. Bhat, S. Ryu*, A. Raychowdhury, "MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-Of-Arrival Estimation"
IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I)
S. Spetalnick, A. Lele, B. Crafton, M. Chang, S. Ryu, J-H. Yoon, Z. Hao, A, Ansari, W-S. Khwa, Y-D. Chih, M-F. Chang, A. Raychowdhury, "An Edge Accelerator with 5MB of 0.256pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance"
IEEE Journal of Solid-State Circuits (JSSC)
S. Ryu, J. Kim, A. Raychowdhury, "Fractionally-Spaced Equalizers as Clock and Data Recovery Loops"
IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I)
A. Assoa, A. Bhat, S. Ryu, A. Raychowdhury, "A Modular, Distributed and Scalable DOA Estimator for MIMO Systems"
IEEE MTT-S International Microwave Symposium (IMS)
S. Konno, Z. Ellis, A. Golder, S. Ryu, D. Dinu, A. Varna, S. Mathew, A. Raychowdhury, "A 65nm Delta-Sigma ADC based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Ditection Capability Down to 0.25ohm"
IEEE Symposium on VLSI Technology and Circuits (VLSI)
S. Spetalnick, A. Lele, B. Crafton, M. Chang, S. Ryu, J-H. Yoon, Z. Hao, A, Ansari, W-S. Khwa, Y-D. Chih, M-F. Chang, A. Raychowdhury, "A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance"
IEEE International Solid-Sate Circuits Conference (ISSCC)
2023
S. Ryu, A. Assoa, S. Konno, A. Raychowdhury, "A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications"
IEEE Symposium on VLSI Technology and Circuits (VLSI)
A. Assoa, A. Bhat, S. Ryu, A. Raychowdhury, "A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems"
ACM GLSVLSI
Up to 2022
S. Ryu, C. Park, W. Kim, S. Son, J. Kim, "A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC"
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
S. Son, S. Ryu, H. Yeo, J. Kim, "A 2x Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery"
IEEE Journal of Solid-State Circuits (JSSC)
S. Ryu, S. Son, J. Kim, "An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops"
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
H. Yeo, S. Ryu, Y. Lee, S. Son, J. Kim, "A 940MHz-Bandwidth 28.8us-Period 8.9 GHz Chirp Frequency Synthesizer PLL in 65nm CMOS for X-Band FMCW Radar Applications"
IEEE International Solid-Sate Circuits Conference (ISSCC)
S. Ryu, H. Yeo, Y. Lee, S. Son, J. Kim, "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function"
IEEE Journal of Solid-State Circuits (JSSC)
S. Ryu, J. Kim, "Cell-Based Construction of Mixed-Signal Systems Using Co-Design Flow of IC Compiler and Custom Designer: A Digital PLL Example"
Proc. Synopsys SNUG
S. Ryu, H. Yeo, Y. Lee, S. Son, J. Kim, "A 9.2 GHz Digital Phase-Locked Loop with Peaking-Free Transfer Function"
IEEE Custom Integrated Circuits Conference (CICC)
K. Kim, S. Son, S. Ryu, H. Yeo, Y. Choi, J. Kim, "A 1.3-mW, 1.6-GHz Digital Delay-Locked Loop with Two-Cycle Locking Time and Dither-Free Tracking"
IEEE Symposium on VLSI Technology and Circuits (VLSI)
J. Kim, S. Ryu, B. Yoo, H. Kim, Y. Choi, D-K. Jeong, "A Model-First Design and Verification Flow Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs"
IEEE International Symposium on Circuits and Systems (ISCAS)
Domestic Technical Papers
박우진, 류시강, "도래각 추정을 위한 분산 MUSIC 프로세서 설계," 대한전자공학회 추계학술대회, Nov. 2024
김두현, 류시강, 김재하, "채널 특성의 조각별 선형근사에 기반한 고속 수신기 연속시간 선형 등화기 회로의 최적 설계방법," 대한전자공학회 추계학술대회, Nov. 2024
International Technical Patents
J. Kim, H. Yeo, S. Ryu, "Synthesizing Method of Signal Having Variable Frequency and Synthesizer of Signal Having Variable Frequency"
US Patent