Shivdeep (शिवदीप)

Physical Design

IC tapeout (1.5 mm x 1.5 mm) using UMC 180 nm CMOS technology

In this project, I have done a complete tapeout, which includes an area and placement plan, pin distribution, I/O pads, and padframe, integration of colleagues' projects, etc. I did the layouts of three EMI immune amplifiers, D1, D2, and IA2, as shown in the central figure, along with three instrumentation amplifiers designed by my colleague, capacitively coupled chopper INA, area-optimized capacitively coupled INA, and CFIA. The testing of the fabricated IC is done, and the IC is 100% successful with all designs functional and meeting the expectations.

(Right to left: packaged IC and bare die, micrograph, EMI immune amplifiers, layout of entire IC;)

Layout of IC with projects from multiple scholars

EMI-immune amplifiers

(Two OTAs D1 and D2, a three-OpAmp INA IA2;)

IC Micrograph

Bare die and packaged IC

A 2x2 resistive crossbar array to demonstrate the reduction in EMI-induced offset (SCL 180 nm CMOS technology)

Area-efficient capacitively coupled neural amplifier (65 dB CMRR for 0.006 mm2) (TSMC 180 nm CMOS technology) (circuit designed by Sahil Sharma)

Full custom layout of Brain-Inspired Spiking Neural Associative Memory (TSMC 180 nm CMOS technology)

(circuit designed by S.K. Vohra)

Full custom layout of Activation Clock Logic circuit for a Dynamic Comparator (UMC 180 nm CMOS technology)

(circuit designed by Nidhi Sharma)

Test boards

IC soldered on PCB to reduce parasitics

IC mounted on socket which is mounted on test board via daughter board

EMI susceptibility testing of commercial OTA ICs in various feedback configs

and

Realization of 2x2 resistive crossbar for EMI susceptibility testing with commercial ICs used as summing amplifiers

Daughter board with 64 pin socket to hold QFP64 IC

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