M. Tech
M. Tech
Embedded Files
VLSI Design
School of VLSI Technology (SOVLSIT)
Indian Institute of Engineering Science and Technology, Shibpur
Botanic Garden, Shibpur, Howrah, West Bengal, India - 711103
Major Project
Major Project
Digital Image Watermarking (DIW) Algorithms and Hardware Implementation
Supervisor: Dr. Sudip Ghosh, (Asst. Prof. click here); Prof. Hafizur Rahaman (click here), SOVLSIT, IIEST, Shibpur;
About: Implemented and optimized the watermarking algorithms on MATLAB, designed a hardware architecture followed by FPGA implementation using Verilog, and ASIC implementation of the same using SCL 180 nm technology.
Skills: Image processing, MATLAB, Verilog, Hardware architecture design, FPGA, ASIC.
Publications:
Shivdeep, S. Ghosh and H. Rahaman, “A New Digital Color Image Watermarking Algorithm with its FPGA and ASIC Implementation,” 2020 International Symposium on Devices, Circuits and Systems (ISDCS), Howrah, India, 2020, pp. 1-6, doi: 10.1109/ISDCS49393.2020.9263003.
Shivdeep, S. Ghosh, T. Nag, S. P. Maity and H. Rahaman, “Reversible Color Image Watermarking Algorithm using Reverse Contrast Mapping,” 2020 IEEE 1st International Conference for Convergence in Engineering (ICCE), Kolkata, India, 2020, pp. 444-447, doi: 10.1109/ICCE50343.2020.9290684.
Shivdeep, S. Ghosh, P. Ghosal, S. P. Maity and H. Rahaman, “PEE Based Reversible Watermarking Algorithm for Authentication and Security of Medical Images,” 2020 IEEE Region 10 Symposium (TENSYMP), Dhaka, Bangladesh, 2020, pp. 1620-1623, doi: 10.1109/TENSYMP50017.2020.9230851.
Shivdeep, A. Biswas, S. Ghosh, T. Nag, S. P. Maity and H. Rahaman, “HLS Based Implementation of Modified DE-RIW Algorithm on FPGA and P-SoC,” 2020 IEEE 1st International Conference for Convergence in Engineering (ICCE), Kolkata, India, 2020, pp. 439-443, doi: 10.1109/ICCE50343.2020.9290711.
Other Projects
Other Projects
Circuit design, simulation, and Physical design
Design & layout of Standard gate library using Cadence IC design tools and standard 40nm technology.
32-bit digital integrator circuit design, layout & post-layout simulation in standard 180nm technology.
ASIC and FPGA-based hardware implementation of 8-bit Booth multiplier. Software level implementation using MATLAB, RTL design & functional verification using Verilog, Synthesis, RTL2GDS.
Courses
Courses
Analog IC Design
VLSI Technology
SoC and Memory Design
VLSI Testing
Synthesis and Verification Techniques
Low Power Design Techniques
Advanced System Architecture
Digital Signal Processing
Semiconductor Physics and Devices
VLSI Physical Design
Cadence Lab Project
Prepared by: Shivdeep
40nm CMOS Technology
email: sivdp1@gmail.com
28jan, 2019
Objectives:
Design, layout, and simulation of a CMOS inverter and some other logic gates.
Design, Layout, and Simulation of CMOS Inverter and some other basic logic circuits
Week1: Inverter, XOR, XNOR;
Week2: NAND, NOR, AOI (AB+C) ;
Week3: TG, DFF using TG;
Week4: MUX using TG;Create two libraries namely Standard_Cell_28nm_JUNK_Name and Standard_Cell_28nm. The correct and final version of the cell will be copied to Standard_Cell_28nm.
All the basic gates must be sized properly taking a load of 8u. All basic gates will be of 2 inputs. MUX will be of 2:1. The DFF must have asynchronous set, reset, positive edge triggered, enable, Master Slave configuration.
Calculate Rise time, Fall time, Delay, Power (Static & Dynamic) of each cell.
Layout must be optimized with DRC, LVS cleaned with the cell height of 18 tracks.
Week 1: Inverter, XOR, XNOR;
Inverter
Transistor sizing: schematic, simulation and calculation
In given schematic width of NMOS is taken 0.48um as reference and that of PMOS is taken as variable 'w'. By parametric analysis we'll obtain value of w at which Inverter gives 50% output at 50% input.
In our case we got, w = 1.236 um ie. Wp:Wn = 2.5625
As given in objective the load to be driven is Cout = 8u
Cout/Cin = 4 (given) => Cin = 2u = Wp + Wn
=> 2.563x + x = 2 say( Wn = x ) Which gives x = 0.560 um (approx..)
Hence we got width as Wp = 1.44 um and Wn= 0.56 um
Now onwards we'll use these parameters to design CMOS Inverter and that Inverter will be used as refernece to desin all other CMOS circuit in this lab work.
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