Shivdeep

Analog IC Design Engineer | Ph.D., IIT Ropar

Vienna, Austria

Specializing in EMI-immune CMOS amplifiers, full-custom analog front-ends, and end-to-end silicon integration from layout to post-silicon characterization. #opentowork

I am an Analog IC Design Engineer. My technical focus is on crafting robust, high-reliability analog circuits, and my professional identity is deeply rooted in collaboration. Having spent years managing research labs and coordinating multi-project tapeout, I’ve learned that I am at my best when I am helping peers troubleshoot complex design blocks and exchange ideas. I have recently completed my Ph.D. at the Indian Institute of Technology (IIT) Ropar. My thesis focuses on enhancing the Electromagnetic Interference (EMI) immunity of amplifiers at the circuit level. I completed the Master's (M.Tech) in VLSI Design at SOVLSIT, IIEST Shibpur, in 2020.

My core research expertise centers on the design and physical integration of high-reliability, EMI-immune analog front-ends. However, I actively seek to apply my design methodologies to the evolving frontiers of architecture. Through rewarding lab collaborations and patent work, my broader research interests have expanded into brain-inspired neuromorphic computing hardware, fault-tolerant crossbar interfaces for edge-AI inference, and integrated hardware security.

Academic background

Ph.D. (Analog IC Design) Indian Institute of Technology Ropar, Punjab, India (2020 - May, 2026)
M.Tech (VLSI Design) IIEST Shibpur, West Bengal, India (2018 - 2020)🔗
B.Tech (ECE) Dr. A.P.J. A. K. Technical University, Lucknow, UP, India (2012 - 2016)
Schooling Jawahar Navodaya Vidyalaya (JNV) Auraiya, UP, India (2005 - 2012)

Technical Highlights at a Glance

Silicon Success

Tapeout Lead: Managed and integrated full-custom multi-project die (1.5 mm x 1.5 mm area).

Process Technology: Hands-on design and tapeout experience in 180 nm CMOS nodes.

Achieved 100% functional success on fabricated ICs, validated through rigorous hardware testing.

Circuit Expertise

EMI-Immune Design: High-reliability, electromagnetic interference (EMI) immune CMOS amplifiers.

Core Sub-Blocks: Operational transconductance amplifiers (OTAs), instrumentation amplifiers (INA), and Crossbar-interface circuits.

Target Applications: Precision sensing and crossbar-based neuromorphic architectures.

Physical Design & Validation

Full-Custom Layout: Sub-micron analog layout (180/65/40 nm), padframe integration, and ESD/ antenna rule compliance.

Physical Verification: Complete sign-off flows, including strict DRC, ERC, LVS, and PEX debugging.

Post-Silicon Testing: Hands-on experience in PCB design, measurements, characterization, and debugging.

Skills

CMOS, Analog, Biasing circuits, Current mirrors, Amplifiers, OTA, INA, EMI, Memristor, SNN, DAC, ADC, Full custom Layout, PDK, Sign off, Tapeout, PCB, Testing, Cadence Virtuoso, Calibre, Assura, MATLAB, Verilog, Linux, RedHat, CentOS, RTL, FPGA, Instruments, Teaching, Management, Mentorship, Technical Writing, English.

IC Design

Analog & Mixed-Signal: CMOS Analog IC Design, Beta multiplier, Current mirrors, OTA, Amplifiers, and three-OpAmp INA.
Specialized Architectures: EMI Immune Amplifiers, SNN, and Crossbar circuits for neuromorphic computing.
Emerging Technologies: Memristive circuits, Trainable data converter, foundational understanding of FinFET.
Digital & System-Level: Digital IC Design, Data Converters, Algorithm-to-RTL, Verilog, FPGA, and ASIC.

Physical Design, Sign-Off & Tapeout

Full-Custom Layout: Analog/Mixed-Signal sub-micron layout, Guard Ring, Device Matching techniques (Common-Centroid, Interdigitation).
Top-Level Chip Integration: Full-die Floorplanning, Padframe Design, Pin Distribution, ESD cells, and Antenna Rule.
Physical Verification (Sign-Off): Complete execution of DRC, LVS, ERC, PEX, and debugging.

EDA Tools & Software

IC Design & Verification: Cadence Virtuoso, Calibre, and Assura.
Linux-based systems (Red Hat, CentOS, Ubuntu), license server management, and remote client environment setup for Cadence tools.
MATLAB, Verilog.
Set up the Open-Source Toolchains: Xschem, Ngspice, gnuplot, Magic, and SkyWater PDK.
Cadence Innovus, Genus, and Xilinx ISE. (during masters)

Post-Silicon Validation & Instrumentation

PCB Design: Full custom mother and daughter board and design using EasyEDA tools, including SMD soldering and rework.
Laboratory experiments: Test and characterization of fabricated silicon.
Instruments: Hands-on operation of RF Signal Sources, Bias Tee, Signal Analyzers, Oscilloscopes, Function Generators, high-precision SMU, 6.5-digit DMM.

Lab Management & Academic Contributions

Lab Infrastructure Management: 5 years of experience managing a research lab, record keeping & maintaining technical resources, and administering EDA tool design environments.
Teaching Assistantship: Assisted faculty in delivering undergraduate and postgraduate laboratory courses. Managed resources, prepared tutorials, designed test papers, and conducted student evaluations.
Academic Mentorship: Mentored and guided technical execution for multiple Bachelor's and Master's thesis projects.

Research interests🔗

CMOS Analog Integrated Circuits
EMI-immune amplifiers
Crossbar-based circuits
Neuromorphic circuits - SNN
Embedded systems

Courses credited during Ph.D.

CMOS Analog IC Design
Circuit Simulation Lab
Digital IC Design
Low Power Design
Mixed Signal IC Design
Broadband Circuit Design

Teaching assistantship

Circuit Simulation Lab (PG)
Analog Circuits Lab
Basic Electronics Lab
Principles of Electrical Engineering Lab 🔗

Selected Publications🔗

Shivdeep, S. Sharma, M. Sakare and D. M. Das, "Mitigating EMI Susceptibility in Three OpAmp INA With a High CMRR EMI Immune OTA," in IEEE Transactions on Electromagnetic Compatibility, doi: 10.1109/TEMC.2026.3677893.
Shivdeep, S. Boyapati and D. M. Das, “Impact of EMI on the Reliability of Crossbar Architecture-based Inference in CMOS Technology," in IEEE Transactions on Components, Packaging and Manufacturing Technology, doi: 10.1109/TCPMT.2025.3559486.
S. K. Vohra, S. A. Thomas, Shivdeep, M. Sakare and D. M. Das, “Full CMOS Circuit for Brain-Inspired Associative Memory with On-Chip Trainable Memristive STDP Synapse,” in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, doi: 10.1109/TVLSI.2023.3268173.
Shivdeep, S. Sharma, S. Boyapati and D. M. Das, “A Two Stage Miller OpAmp with Low Voltage Cascode Current Source with High EMI Immunity," 2023 International Symposium on Electromagnetic Compatibility – EMC Europe, Krakow, Poland, 2023, pp. 1-6, doi: 10.1109/EMCEurope57790.2023.10274391.
D. Chowdhury, Shivdeep, and D. M. Das, “A Pulse Oximeter and a Controller Designed for Automatic Regulation of Oxygen Concentrators,” 2024 37th International Conference on VLSI Design (VLSID), Kolkata, India, 2024, pp. 336-341, doi: 10.1109/VLSID60093.2024.00062.
S. Chittoriya, Shivdeep, K. K. Jha, D. M. Das and R. Sharma, “A Low-Overhead PUF-Based Hardware Security Technique to Prevent Scan Chain Attacks for Industry-Standard DFT Architecture,” 2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS), Fukuoka, Japan, 2022, pp. 1-4, doi: 10.1109/MWSCAS54063.2022.9859268.
Shivdeep, S. K. Vohra, N. Goel and D. M. Das, “A Robust Training Signal Generator for Trainable Memristive Digital to Analog Converter,” 2021 IEEE International Symposium on Smart Electronic Systems (iSES), Jaipur, India, 2021, pp. 1-5, doi: 10.1109/iSES52644.2021.00014.

Click here to see all publications

Patent

Indian Patent Application No. 202511026465, "A crossbar interfacing circuit immune to electromagnetic interference (EMI)", Shivdeep, S. Sharma, D. M. Das.

Page updated

Report abuse