Dr. Gopal R. Raut, Knowledge Associate
Affiliation: Center for Development of Advanced Computing (C-DAC) Bangalore, Ministry of Electronics and Information Technology (MeitY), Govt. of India
Research : Optimizing Hardware Architectures: SoC Design Innovations for DNN Accelerators
About Me : I obtained my M.Tech. degree in VLSI Design from G H Raisoni College of Engineering Nagpur, India, in 2015, and completed my Ph.D. degree in 2022 from the Electrical Engineering Department, Indian Institute of Technology Indore, India. During my doctoral studies, I also worked as a guest researcher at TU Dresden, Germany. Currently, I am working as a Knowledge Associate with C-DAC India, focusing my research on compute-efficient and configurable VLSI circuit design for IoT and edge-AI applications.
About C-DAC Bangalore: Secure Hardware and VLSI Design (SHVD)
About my Ph.D Lab: Nanoscale Devices, VLSI Circuit and System Design Lab (NSDCS)
About my Research
About My Research: Greetings and welcome to my research page. It is my pleasure to present to you my research interests in the field of digital circuit design. With a particular focus on DNN accelerators, FPGA implementation, ASICs for Edge-AI and the intricacies of hardware-software co-design, I am dedicated to advancing the frontiers of innovation. Kindly explore the following key points to gain deeper insights into my research endeavors and contributions.
Unveiling Research Portfolio
1. Efficient Arithmetic Module Design:
Developing innovative arithmetic modules using CORDIC architecture, POSIT/Bfloat16/Fixed-point arithmetic, and MAC units.
Enhancing the performance and accuracy of MAC, AFs computing blocks and DNN accelerators; RISC-V Archi Exploration.
2. Software-Hardware Co-validation:
Designing software platforms to validate hardware performance accurately using Python libraries.
Creating comprehensive validation frameworks for reliable and efficient DNN accelerators, DMA controller architecture.
3. VLSI Design and Layout:
CMOS circuit design for in-memory computing using SRAM, mixed-signal VLSI, Amplifiers/Comparators, and ADCs.
Layout design using CMOS technology, applying DRC-LVS-PEX techniques at 45nm/180nm nodes, and successful tapeout processes.
4. ASIC Design Flow:
Proficiency in the entire ASIC design flow, from conceptualization to GDS-II, ensuring efficient circuit integration.
Explore my research interests in In-Memory Computing Archi., efficient digital circuit design for DNN accelerators, software-hardware co-validation, CMOS-VLSI design, and ASIC flow.
Fig: Block design of system architecture with the use of AXI interconnects. The proposed design DNN IP (Annip_0) is shown in orange color whereas Processing system (PL) is used for external communication.
