Education
B.Tech (ECE): IIT Kharagpur (2012)
M.S. (ECE): Georgia Tech (2013)
PhD (ECE): Georgia Tech (2017)
Experience
Assistant Professor, ECE, IIT Bhubaneswar, Dec 2025 onwards
Visiting Assistant Professor, SECS, IIT Bhubaneswar, Jun-Dec 2025
Staff FPGA Silicon Design Engineer, Intel (Altera), Hillsboro, USA, 2021-2025
Senior SoC Design Engineer, Intel, Hillsboro, USA, 2017-2021
Research Intern, Globalfoundries, Santa Clara, USA 2015-16
Sandeep Kumar Samal (S’12-M’17-SM’23) received the B.Tech. degree in Electronics and Electrical Communication Engineering from the Indian Institute of Technology Kharagpur, Kharagpur, India, in 2012, and the Ph.D. degree in Electrical and Computer Engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2017. From 2017 to 2025, he worked at Intel, Oregon, USA, first in the Foundry Technology Development group and then in the Altera FPGA Technology Engineering group. In the Foundry Technology Development group, he was involved in design-technology co-optimization and technology integration for Intel advanced-node processes in next-generation products, specifically in process-monitoring circuit design and analysis, and power-performance-area (PPA) optimization. His FPGA-related work focused on technology pathfinding, system-level packaging exploration, and advanced node test-chip design for next-generation FPGAs and related products. He joined IIT Bhubaneswar in 2025, where he is currently an Assistant Professor in the Department of Electronics and Communication Engineering, School of Electrical and Computer Sciences. His research interests include system- and design-technology co-optimization (STCO/DTCO), CAD for low-power and reliable digital design, 3D ICs, and advanced packaging techniques for digital and power electronics. His Ph.D. research focused on the design and CAD of low-power, reliable monolithic 3D ICs. He also interned at Globalfoundries for one year, working on 3D IC pathfinding and exploration. He is a Senior Member of IEEE and has served as co-chair and member on the Technical Program Committee of several premier conferences in VLSI Design and EDA.