Embedded Files
§ Energy Efficient Wireless Network-on-Chip Architectures
Networks-on-Chip (NoCs) have been accepted as scalable and efficient communication backbone for many-core Systems-on-Chip (SoCs) by both the academia and the industry. However, the traditional approaches of implementing a NoC with planar metal interconnects have high latency and significant power consumption overhead. This is mainly due to the multi-hop links used in data exchange, specifically when the number of cores is significantly high. To address these problems, multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the energy efficient design of wireless NoCs using suitable on-chip wireless transceivers.
§ Network-on-Chip Simulator
New designs containing large numbers of embedded cores are emerging from consumer multimedia to image processing to defense applications, a trend that will undoubtedly continue. These diverse applications will benefit from the multi-core System-on-Chip (SoC) and emerging interconnect architectures, which reduces performance-limiting multi-hop communication in conventional wired Network-on-Chips (NoCs). The innovative multi-core solutions with diverse interconnection topologies will require a platform for quick evaluation and performance analysis. A simulation tool that examines the design quality of future multi-core NoC architecture and provides performance limits is a must for the designers.
§ Efficient Network-on-Chip Router Architecture
Network-on-Chip (NoC) has been well accepted for energy efficient on-chip communications for many-core systems. But, a NoC router consumes significantly high power and the number of routers increases linearly with number of cores. For large scale applications, the cumulative power dissipation in routers is comparatively high. Of all router components, input buffers consume significant amount of power. Additionally, removing buffers from NoC router leads to performance degradation and network congestion overhead.
§ On-Chip Wireless Channel Modeling
Networks-on-Chip (NoCs) with long range wireless links have been proven to address the issues associated wired interconnects in long range communication on chip. The delay and energy per bit consumption with wireless interfaces (WIs) is less than one-tenths of that with their wired counterparts. But these values are obtained by assuming an ideal free space communications between WIs which is not the case. The wireless communication on-chip is effected by different interference structures like substrate, metal interconnects, etc. To analyze these effects, we model the on-chip environment using different models and simulate the electromagnetic propagation between two antennas. The focus is to find the adverse effects on on-chip propagation and then come up with solutions to decrease the propagation delay, increase signal strength, reliability and improve the performance of the on-chip wireless interconnects.
§ Preventive Health Care Device
Human body circulatory system to be composed collectively of the cardiovascular system, which distributes blood, and the lymphatic system. The essential components of the human cardiovascular system are the heart, blood, and blood vessels. It includes: the circulation. There are lot many diseases caused because of abnormality of our cardiovascular system such as stress, Heart failure, Arrhythmia, Heart valve problems etc. A psychophysiological monitoring system for cardiovascular disease measurement is needed because of multifarious influences of cardiovascular disease on the psychological response of the body. In a study we investigated how to take cardiac signal (ECG, PPG, PCG) and extract features from that signals. Our study at developing and testing of cardiac signal monitoring is based on different platform like Raspberry pi based stand alone cardiac monitor, android mobile and tablet based solution and PC based window app to monitor real time cardiac signals. It gives useful information like electrical signals of the heart (ECG), the condition of the arteries (PPG), Oxygen saturation in blood (SpO2) and arterial pressure of the systemic circulation (BP).The device will collect and make storage of preliminary health data, transmit the data using conventional network connectivity, create health database, map the disease and improve detection and treatment rates to fetch significant health benefits. This developed system seems to be a valid, low cost, easy to use and can be accepted as an alternative to the existing devices in the market.
§ System Validation
The huge time requirement for the thorough validation of complex integrated circuits using extensive simulation and formal verification in the pre-silicon stage is unbearable and introduces the threat of missing the time to market. This has encouraged the silicon debug technique to find out the undetected design bugs as soon as the first silicon is available. Silicon debug includes two steps known as (i) data acquisition and (ii) analysis. The major challenges in the silicon debug data acquisition stage can be primarily faced at two levels as follows: (i) Storing the huge trace data (limited trace buffer size), (ii) Low bandwidth off-chip interface to transfer the sampled trace data. Moreover, the debug structure becomes vestigial once the product validation phase is over. In this context, our research work proposes a wireless-enabled debug structure for faster trace communication, a redundant trace elimination mechanism for efficient trace reduction and reuse of trace buffer as routers’ virtual channel for system performance improvement.
§ Hardware Security
Increasing demand for high performance and energy efficiency along with time-to-market pressures have led to a growing number of optimized third-party Intellectual Property (IP) blocks in modern System-on-Chips (SoCs). However, the third-party IPs may introduce vulnerabilities due to malicious intent or elusive design bugs that escape through verification processes. These vulnerabilities can be exploited by various attackers which can corrupt the entire system. In our research works we target various security aspects in emerging heterogenenous architectures. We address the flooding-based Denial-of-Service (DoS) attacks that can be triggered by a Malicious IP (MIP) to obstruct on-chip network communication by injecting useless packets. To secure the SoCs from flooding attacks, we propose attack detection and localization frameworks that leverage machine learning (ML) models to detect an attack scenario and localize one or multiple MIPs.
§ Domain-specific architectures
In recent years, the demand for high-performance and energy-efficiency has led the embedded systems towards domain-specific customized designs, commonly known as hardware accelerators. The overwhelming performance improvement achieved from hardware acceleration has spurred a growing number of fixed-function accelerators in modern System-on-Chips (SoCs). However, as the number of such fixed-function accelerators increases, the available on-chip resource budget becomes a major bottleneck due to the stringent design constraints of embedded systems. In our research work, we address the challenges involved in designing efficient accelerator-rich domain-specific SoCs. We also propose design solutions to accelerate the widely used Convolutional Neural Network (CNN) algorithms.
Research_work.mp4Page updated
Report abuse