Buses

Buses are a set of parallel wires which connect two or more components inside the CPU. There are three buses in the CPU: data bus, control bus, and address bus. These buses collectively are called the system bus. The width of the bus is the number of parallel wires the bus has.

The width of the bus is directly proportional to the number of bits that can be transferred simultaneously at any given time. buses are typically 8, 16, 32 or 64 wires wide.

This is a bi-directional bus used to transmit control signals between internal and external components. The control bus coordinates the use of the address and data buses and provides status information between system components.

The control signals include:

• Bus request: shows that a device is requesting the use of the data bus

• Bus grant: shows that the CPU has granted access to the data bus

• Memory write: data is written into the addressed location using this bus

• Memory read: data is read from a specific location to be placed onto the data bus,

• Interrupt request: shows that a device is requesting access to the CPU

• Clock: used to synchronise operations

Pipelining

Pipelining is the process of completing the fetch, decode, and execute cycles of three separate instructions simultaneously, holding appropriate data in a buffer in close proximity to the CPU until it’s required. While one instruction is being executed, another can be decoded and another fetched.

Fetch-Decode-Execute Cycle and Registers

The fetch-decode-execute cycle is the sequence of operations that are completed in order to execute an instruction.

Fetch phase:

• Address from the PC is copied to the MAR

• Instruction held at that address is copied to MDR by the data bus

• Simultaneously, the contents of the PC are increased by 1

• The value held in the MDR is copied to the CIR

Decode phase:

• The contents of CIR are split into operand and opcode

Execute phase:

• The decoded instruction is executed

Factors affecting CPU performance

There are three factors that affect CPU performance: clock speed, number of cores and the amount and type of cache memory.

Clock speed

The clock speed is determined by the system clock. This is an electronic device which generates signals, switching between 0 and 1. All processor activities begin on a clock pulse, and each CPU operation starts as the clock changes from 0 to 1. The clock speed is the time taken for one clock cycle to complete.

Number of cores

A core is an independent processor that is able to run its own fetch-execute cycle. A computer with multiple cores can complete more than one fetch-execute cycle at any given time. A computer with dual cores can theoretically complete tasks twice as fast as a computer with a single core. However, not all programs are able to utilise multiple cores efficiently as they have not been designed to do so, so this is not always possible.

Amount and type of Cache Memory

Cache memory is the CPU’s onboard memory. Instructions fetched from the main memory are copied to the cache, so if required again, they can be accessed quicker. As cache fills up, unused instructions are replaced.

Cache Level 1 - Small data capacity but super fast

Cache Level 2- medium-size data capacity and relatively fast

Cache Level 3 - lager capacity of data much slower compared to Cache Level 2 and Level 1.

Computer Architecture

Von Neumann Architecture

This architecture includes the basic components of the computer and processor (single control unit, ALU, registers, and memory units) in which shared memory and shared data bus is used for both data and instructions. Von Neumann architecture is built on the stored program concept.

Harvard Architecture

Harvard architecture has physically separate memories for instructions and data, more commonly used with embedded processors. This is useful when memories have different characteristics, i.e. instructions may be read only, while data may be read-write. This also allows you to optimise the size of individual memory cells and their buses depending on your needs, i.e. the instruction memory can be designed to be larger so a larger word size can be used for instructions

PAST PAPER QUESTIONS

Try and answer the past paper exam questions -You can write your answers on paper or print out the exam paper - Mark Scheme is provided at the end of the paper questions. (try not to look at the answers before attempting all questions)