Publications

CONFERENCE PAPERS

1. C.-W. Wu, P. R. Cappello, and Michael Saboff, "An FIR filter tissue", in Proc. IEEE 19th Asilomar Conf. on Circuits, Systems, and Computers, Pacific Grove, Nov. 1985, pp. 283~287.

2. C.-W. Wu and P. R. Cappello, "Application specific CAD of high-throughput IIR filters", in Proc. 32nd IEEE COMPCON, San Francisco, Feb. 1987, pp. 302~305.

3. C.-W. Wu and P. R. Cappello, "COMPUTER-AIDED DESIGN OF VLSI SECOND-ORDER SECTIONS", in Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), Dallas, Apr. 1987, pp. 1907~1910.

4. C.-W. Wu, "Test generation for combinational iterative logic arrays", in Proc. 3rd Int. Symp. on IC Design and Manufacturing (ISIC), Singapore, Sept. 1989, pp. 223~230.

5. C.-W. Wu, "BLOCK PIPELINE 2-D IIR FILTER STRUCTURES VIA ITERATION AND RETIMING", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), New Orleans, May 1990, pp. 731~734.

6. C.-W. Wu, S.-K. Lu, and J.-C. Wang, "Built-in self-test of iterative logic arrays", in Proc. Int. Electron Devices and Material Symp. (EDMS), Hsinchu, Nov. 1990, pp. 485~488.

7. K.-J. Lin and C.-W. Wu, “On easily testable array multipliers”, in Proc. Int. Computer Symp. (ICS), Hsinchu, Dec. 1990, pp. 571~576.

8. C.-Y. Lin, Y.-R. Shieh, and C.-W. Wu, "A CMOS 1-out-of-3 totally self-checking checker", in Proc. Int. Symp. on IC Design and Manufacturing (ISIC), Singapore, Sept. 1991, pp. 129~134.

9. T.-Y. Chang, C.-W. Wu, C.-C. Wang, and J.-B. Shu, "On the design of a fault-tolerant systolic array multiplier using time redundancy", in Proc. Int. Symp. on IC Design and Manufacturing (ISIC), Singapore, Sept. 1991, pp. 497~502.

10. C.-W. Wu and S.-K. Lu, "Architecture-specific computer-aided testing", in Proc. Sino-German CAD/VLSI Workshop, Tainan, Sept. 1991, pp. 34~43.

11. C.-W. Wu and S.-K. Lu, "Designing Self-Testable Cellular Arrays", in Proc. IEEE Int. Conf. on Computer Design (ICCD), Cambridge, Massachusetts, Oct. 1991, pp. 110~113.

12. J.-C. Wang and C.-W. Wu, "A bit-level systolic block FIR filter chip with built-in self-test structure", in Proc. Int. Symp. on Communications, Tainan, Dec. 1991, pp. 660~663.

13. S.-K. Lu, C.-W. Wu, and S.-Y. Kuo, "Testable design of systolic arrays for discrete Cosine transform", in Proc. 1992 VLSI/CAD Workshop, Nantou, Mar. 1992, pp. 228~237.

14. C.-W. Wu and J.-C. Wang, "Testable Design of Bit-Level Systolic Block FIR Filters", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), San Diego, May 1992, pp. 1129~1132.

15. S.-K. Lu, C.-W. Wu, and S.-Y. Kuo, "Design of Easily Testable VLSI Arrays for Discrete Cosine Transform", in Proc. IEEE 26th Ann. Asilomar Conf. on Signals, Systems, and Computers, Pacific Grove, Oct. 1992.

16. C.-W. Wu, C.-T. Chang, and T.-Y. Chang, "On testable design of FFT butterfly networks", in 1992 Int. Conf. on Parallel and Distributed Systems (ICPADS), Hsinchu, Dec. 1992, pp. 190~195.

17. Y.-R. Shieh and C.-W. Wu, "A totally self-checking checker for CMOS stuck-on faults", in Proc. Int. Computer Symp. (ICS), Taichung, Dec. 1992, pp. 1093~1099.

18. Y.-F. Chou and C.-W. Wu, "Realization of a practical cellular divider", in Proc. Int. Computer Symp. (ICS), Taichung, Dec. 1992, pp. 1078~1084.

19. Y.-R. Shieh and C.-W. Wu, "Concurrent Error Detection of CMOS Digital and Analog Faults", in Proc. European Test Conference (ETC), Rotterdam, Apr. 1993, pp. 74~81.

20. C.-W. Wu and H.-S. Chen, "Modular-Addit ion Signature Analysis for Built-in Self-Test", in Proc. European Test Conference (ETC), Rotterdam, Apr. 1993, pp. 457~465.

21. Y.-L. Li and C.-W. Wu, "Cellular automata for efficient parallel fault simulation", in Proc. 4th VLSI Design/CAD Workshop, Nantou, Aug. 1993, pp. 181~185.

22. C.-W. Wu and H.-S. Chen, "Cost-effective signature analysis by modular counters", in Proc. 4th VLSI Design/CAD Workshop, Nantou, Aug. 1993, pp. 216~220.

23. W.-F. Chang and C.-W. Wu, "Totally self-checking checkers for m-out-of-n code with lower hardware complexity", in Proc. 4th VLSI Design/CAD Workshop, Nantou, Aug. 1993, pp. 226~230.

24. W.-F. Chang and C.-W. Wu, "Design of Efficient Totally Self-checking Checkers for m-out-of-n Code", in Proc. 2nd IEEE Asian Test Symp. (ATS), Beijing, Nov. 1993, pp. 281~286.

25. Y.-L. Li and C.-W. Wu, "Logic and Fault Simulation by Cellular Automata", in Proc. European Design and Test Conf. (ED&TC), Paris, Feb. 1994, pp. 552~556.

26. Y.-L. Li and C.-W. Wu, "Logic and fault simulation by massive parallelism", in Proc. NCHC High-Speed Computing Application Workshop, Hsinchu, Apr. 1994, pp. 195~198.

27. S.-M. Kao, T. Ning, C.-W. Wu, and H. Peng, "Extraction of the Focused Object in an Image by Filtering out the Defocused Background", in Proc. IEEE Int. Symp. on Speech, Image Processing, and Neural Networks, Hong Kong, Apr. 1994.

28. C.-W. Wu and Y.-F. Chou, "General Modular Multiplication by Block Multiplication and Table Lookup", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), London, May 1994, pp. 295~298.

29. W.-F. Chang and C.-W. Wu, "Is there a combinational TSC checker for 1/3 code?", in Proc. 5th VLSI Design/CAD Symp., Tainan, Aug. 1994, pp. 199~204.

30. K.-J. Lin and C.-W. Wu, "An area-efficient realization of Exclusive-OR sum-of products expressions", in Proc. 5th VLSI Design/CAD Symp., Tainan, Aug. 1994, pp. 143~148.

31. C.-H. Tsai, J.-H. Hong, and C.-W. Wu, "Built-in self-test techniques using Boundary Scan Standard circuitry", in Proc. 5th VLSI Design/CAD Symp., Tainan, Aug. 1994, pp. 257~262.

32. F.-D. Guo, J.-H. Hong, and C.-W. Wu, "Automatic generation of Boundary Scan and BIST circuitry", in Proc. 5th VLSI Design/CAD Symp., Tainan, Aug. 1994, pp. 251~256.

33. S.-K. Lu, S.-Y. Kuo, and C.-W. Wu, "Design and Evaluation of Fault-Tolerant Interleaved Memory Systems", in Proc. 3rd IEEE Asian Test Symp. (ATS), Nara, Nov. 1994, pp. 354~359.

34. Y.-L. Li, Y.-C. Lai, and C.-W. Wu, "A cellular-automata chip for fast logic and fault simulation", in Proc. Workshop on CPU Research and Development, Hsinchu, May 1995, pp. 125~130.

35. C.-T. Huang and C.-W. Wu, "High-speed C-testable bit-level systolic arrays for GF(2m) inversion", in Proc. 6th VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 136~139.

36. S.-A. Hwang and C.-W. Wu, "Area-efficient high-speed systolic arrays for Lempel-Ziv data compression", in Proc. 6th VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 212~215.

37. W.-F. Chang and C.-W. Wu, "Design of TSC Berger code checkers for (2r-1)-bit information", in Proc. 6th VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 132~135.

38. C.-Y. Su and C.-W. Wu, "A practical VLSI architecture for RSA public-key cryptosystem", in Proc. 6th VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 273~276.

39. K.-J. Lin and C.-W. Wu, "A Low-Cost Realization of Multiple-Input Exclusive-OR Gates", in Proc. 8th Annual IEEE Int. ASIC Conf., Austin, Sept. 1995, pp. 307~310.

40. Y.-R. Shieh and C.-W. Wu, "DC Control and Observation Structures for Analog Circuits", in Proc. 4th IEEE Asian Test Symp. (ATS), Bangalore, Nov. 1995, pp. 120-126, (Reprinted in the 10th Anniversary Compendium of Papers from ATS, pp. 112-118, IEEE, 2001).

41. S.-K. Lu, C.-W. Wu, and S.-Y. Kuo, "ON FAULT-TOLERANT FFT BUTTERFLY NETWORK DESIGN", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Atlanta, May 1996, pp. 69~72.

42. P.-S. Chen, S.-A. Hwang, and C.-W. Wu, "A SYSTOLIC RSA PUBLIC KEY CRYPTOSYSTEM", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Atlanta, May 1996, vol. 4, pp. 408~411.

43. Y.-R. Shieh and C.-W. Wu, "DFT structures for IEEE P1149.4-compatible integrated circuits", in Proc. 2nd IEEE Int. Mixed Signal Testing Workshop, Quebec city, May 1996, pp. 210~215.

44. W.-F. Chang and C.-W. Wu, "A TSC Berger code checker for (2r-1)-bit information", in Proc. 2nd IEEE Int. On-Line Testing Workshop, Biarritz, July 1996, pp. 158~161.

45. K.-J. Lin and C.-W. Wu, A low-power CAM design in LZ data compressors", in Proc. 7th VLSI Design/CAD Symp., Taoyuan, Aug. 1996, pp. 225~228.

46. H.-C. Hong, S.-H. Shieh, and C.-W. Wu, "Optimization of the spanning tree carry lookahead adder", in Proc. 7th VLSI Design/CAD Symp., Taoyuan, Aug. 1996, pp. 253~256.

47. J.-H. Hong, S.-A. Hwang, and C.-W. Wu, "AN FPGA-BASED HARDWARE EMULATOR FOR FAST FAULT EMULATION", in Proc. Midwest Symp. on Circuits and Systems, Ames, IA, Aug. 1996, vol. 1, pp. 345~348.

48. J.-H. Hong, C.-H. Tsai, and C.-W. Wu, "Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module", in Proc. 5th IEEE Asian Test Symp. (ATS), Hsinchu, Nov. 1996, pp. 50~55.

49. B.-H. Lin, S.-H. Shieh, and C.-W. Wu, "An MISR Computation Algorithm for Fast Signature Simulation", in Proc. Fifth IEEE Asian Test Symp. (ATS), Hsinchu, Nov. 1996, pp. 213~218.

50. C.-T. Huang and C.-W. Wu, "VLSI design of a high speed pipelined Reed-Solomon CODEC", in Proc. Int. Symp. on Multi-Technology Inform. Processing (ISMIP), Hsinchu, Dec. 1996, pp. 517~522.

51. S.-H. Shieh, B.-H. Lin, and C.-W.Wu, "Carry-propagation-free adder based on an asymmetric high-radix signed-digit number system", in Proc. Int. Computer Symp. (ICS), Kaohsiung, Dec. 1996, pp. 199~204.

52. H.-C. Hong, B.-H. Lin, and C.-W. Wu, "Analysis and Design of Multiple-Bit High-Order Σ-∆ Modulator", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Chiba, Jan. 1997, pp. 419~424.

53. C.-T. Huang and C.-W. Wu, "High-speed C-Test able Systolic Array Design for Galois-Field Inversion", in Proc. European Design and Test Conf. (ED&TC), Paris, Mar. 1997, pp. 342~346.

54. S.-A. Hwang and C.-W. Wu, "Low-Power Testing for C-testable Iterative Logic Arrays", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, June 1997, pp. 355~358.

55. C.-L. Lee, J.-Y. Jou, C.-S. Lin, J.-E. Chen, C.-W. Wu, K.-J. Lee, and C.-C. Su, "A joint project to develop a VLSI testing and design for testability course for universities in Taiwan", in Proc. Int. Conf. on Engineering Education (ICEE), Vol. II, Chicago, Aug. 1997, pp. 43~53.

56. S.-A. Hwang and C.-W. Wu, "C-testable systolic array design for LZ data compression", in Proc. 8th VLSI Design/CAD Symp., Nantou, Aug. 1997, pp. 81~84.

57. Y.-C. Chuang and C.-W. Wu, "Concurrent error detection for a systolic Galois-field inverter", in Proc. 8th VLSI Design/CAD Symp., Nantou, Aug. 1997, pp. 77~80.

58. H.-C. Hong and C.-W. Wu, "Optimal integrator gain design of extended MASH high-order Σ-∆ modulator", in Proc. 8th VLSI Design/CAD Symp., Nantou, Aug. 1997, pp. 333~336.

59. C.-W. Wu and C.-C. Wei, "The economic models for a VLSI test strategy planning system", in Proc. SEMICON Taiwan 97, Test Seminar, Taipei, Sept. 1997, pp. 87~92.

60. Y.-R. Shieh and C.-W. Wu, "Logic testing of switch-level faults for CMOS unate networks", in Proc. 7th Int. Symp. on IC Technology, Systems & Applications (ISIC), Singapore, Sept. 1997, pp. 212~215.

61. S.-K. Lu and C.-W. Wu, "VLSI design of the RSA public-key cryptosystem", in Proc. 7th Int. Symp. on IC Technology, Systems & Applications (ISIC), Singapore, Sept. 1997, pp. 68~71.

62. C.-W. Wu, "On Energy Efficiency of VLSI Testing", in Proc. 6th IEEE Asian Test Symp. (ATS), Akita, Nov. 1997, pp. 132~137.

63. S.-A. Hwang and C.-W. Wu, "Minimizing test energy for C-testable iterative logic arrays", in Int. Conf. on Comp. Sys. Technology for Ind. Applications/Chip Technology, Hsinchu, Apr. 1998, pp. 139~145.

64. K.-J. Lin and C.-W. Wu, "Functional Testing of Content-Addressable Memories", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), San Jose, Aug. 1998, pp. 70~75.

65. J.-D. Lin, J.-M. Lu, and C.-W. Wu, "An improved VLSI test economics analysis system", in Proc. 9th VLSI Design/CAD Symp., Nantou, Aug. 1998, pp. 149~152.

66. C.-P. Su, C.-T. Huang, and C.-W. Wu, "DFT methodologies for a communications processor core", in Proc. 9th VLSI Design/CAD Symp., Nantou, Aug. 1998, pp. 161~164.

67. C.-F. Wu and C.-W. Wu, "Testing function units of dynamic reconfigurable FPGAs", in Proc. 9th VLSI Design/CAD Symp., Nantou, Aug. 1998, pp. 189~192.

68. J.-F. Li, S.-A. Hwang, S.-K. Lu, and C.-W. Wu, "Fault tolerant FFT butterfly network design", in Proc. 9th VLSI Design/CAD Symp., Nantou, Aug. 1998, pp. 403~406.

69. Y.-C. Chuang and C.-W. Wu, "On-Line Error Detection Schemes for a Systolic Finite-Field Inverter", in Proc. 7th IEEE Asian Test Symp. (ATS), Singapore, Dec. 1998, pp. 301~305.

70. C.-W. Wu and C.-Y. Su, "A Probabilistic Model for Path Delay Faults", in Proc. 7th IEEE Asian Test Symp. (ATS), Singapore, Dec. 1998, pp. 70~75.

71. C.-W. Wu, "Testing Embedded Memories: Is BIST the Ultimate Solution?", in Proc. 7th IEEE Asian Test Symp. (ATS), Singapore, Dec. 1998, pp. 516~517.

72. C.-F. Wu and C.-W. Wu, "Testing Interconnects of Dynamic Reconfigurable FPGAs", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Hong Kong, Jan. 1999, pp. 279~282.

73. K.-J. Lin and C.-W. Wu, "PMBC: a programmable BIST compiler for memory cores", in 3rd IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), Dana Point, Apr. 1999, pp. P2.1~P2.6.

74. S.-K. Lu and C.-W. Wu, "A Novel Approach to Testing LUT-Based FPGA’s", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Orlando, May 1999, pp. I173~I177.

75. C.-F. Wu and C.-W. Wu, "Fault Detection and Location of Dynamic Reconfigurable FPGAs", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, June 1999, pp. 215~218.

76. J.-F. Li and C.-W. Wu, "Design for C-diagnosable FFT networks", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 191~194.

77. S.-H. Shieh and C.-W. Wu, "On r's-complement addition and conversion from asymmetric high-radix signed-digit numbers to binary numbers", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 161~164.

78. J.-H. Hong and C.-W. Wu, "A radix-4 cellular array modular multiplier based on Montgomery's algorithm and Booth's algorithm", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 165~168.

79. J.-M. Lu and C.-W. Wu, "Economic analysis of built-in self-test for logic and memory cores", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 203~206.

80. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "Testing configurable LUT-based FPGA's", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 171~174.

81. S.-K. Lu, T.-Y. Lee, and C.-W. Wu, "Defect level prediction using multi-model fault coverage", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 195~198.

82. J.-F. Li and C.-W. Wu, "Testable and Fault Tolerant Design for FFT Networks", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 201~209.

83. C.-F. Wu, C.-T. Huang, and C.-W. Wu, "RAMSES: A Fast Memory Fault Simulator", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Albuquerque, Nov. 1999, pp. 165~173.

84. S.-K. Lu and C.-W. Wu, "Defect Level Prediction Using Multi-Model Fault Coverage", in Proc. 8th IEEE Asian Test Symp. (ATS), Shanghai, Nov. 1999, pp. 301~306.

85. J.-H. Hong and C.-W. Wu, "Radix-4 Modular Multiplication and Exponentiation Algorithms for the RSA Public-Key Cryptosystem", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2000, pp. 565~570.

86. C.-T. Huang, J.-R. Huang, and C.-W. Wu, "A Programmable Built-In Self-Test Core for Embedded Memories", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2000, pp. 11~12, (Design contest).

87. J.-M. Lu and C.-W. Wu, "Cost and Benefit Models for Logic and Memory BIST", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Paris, Mar. 2000, pp. 710~714.

88. C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, "Simulation-Based Test Algorithm Generation for Random Access Memories", in Proc. IEEE VLSI Test Symp. (VTS), Montreal, Apr. 2000, pp. 291~296.

89. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "Built-In Self-Test and Fault Diagnosis for Lookup Table FPGAs", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Geneva, May 2000, pp. I.80~I.83.

90. J.-H. Hong, P.-Y. Tsai, and C.-W. Wu, "Interleaving schemes for a systolic RSA public-key cryptosystem based on an improved Montgomery's algorithm", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 163~166.

91. C.-H. Wu, J.-H. Hong, and C.-W. Wu, "An RSA cryptosystem based on the Chinese Remainder Theorem", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 167~170.

92. S.-H. Shieh and C.-W. Wu, "Carry-free adder design using asymmetric high-radix signed-digit number system", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp.183~186.

93. K.-L. Cheng and C.-W. Wu, "Neighborhood pattern-sensitive fault testing for semiconductor memories", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 401~404.

94. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "BIST and diagnosis of fully logic blocks in FPGAs", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 413~416.

95. C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, "BRAINS: A BIST Compiler for Embedded Memories", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Yamanashi, Oct. 2000, pp. 299~307.

96. C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, "Error Catch and Analysis for Semiconductor Memories Using March Tests", in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468~471.

97. J.-R. Huang, C.K. Ong, K.T. Cheng, and C.-W. Wu, "An FPGA-based Re-configurable Functional Tester for Memory Chips", in Proc. 9th IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 51~57.

98. C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, "A Built-In Self-Test and Self-Diagnosis Scheme for Embedded SRAM", in Proc. 9th IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 45~50.

99. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "A Testable/Fault-Tolerant FFT Processor Design", in Proc. 9th IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 429~433.

100. L. Li, X. Yu, C.-W. Wu, and Y. Min, "A Waveform Simulator Based on Boolean Process", in Proc. Ninth IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 145~150.

101. C.-H. Tsai and C.-W. Wu, "Processor-Programmable Memory BIST for Bus-Connected Embedded Memories", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 325~330.

102. C.-H. Wu, J.-H. Hong, and C.-W. Wu, "RSA Cryptosystem Design Based on the Chinese Remainder Theorem", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 391~395.

103. J.-F. Li and C.-W. Wu, "Memory Fault Diagnosis by Syndrome Compression", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Munich, Mar. 2001, pp. 97~101.

104. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, "Using Syndrome Compression for Memory Built-In Self-Diagnosis", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, Apr. 2001, pp. 303~306.

105. K.-L. Cheng, M.-F. Tsai, and C.-W. Wu, "Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories", in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, Apr. 2001, pp. 225~230.

106. C.-F. Wu, C.-T. Huang, K.-L. Cheng, C.-W. Wang, and C.-W. Wu, "Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories", in Proc. IEEE/ACM Design Automation Conf. (DAC), Las Vegas, June 2001, pp. 301~306.

107. Y.-C. Lin, C.-P. Su, C.-W. Wang, and C.-W. Wu, "A word-based RSA public-key crypto-processor core", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.

108. H.-J. Huang, J.-F. Li, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I Chen, C.-Y. Hwang, and H.-P. Lin, "Test wrapper design automation for system-on-chip", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.

109. J.-B. Chen, J.-F. Li, H.-J. Huang, C.-P. Su, C.-W. Wu, C. Cheng, S.-I Chen, C.-Y. Hwang, and H.-P. Lin, "A test controller for system-on-chip designs with test wrappers", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.

110. H.-C. Kao, M.-F. Tsai, S.-Y. Huang, C.-W. Wu, W.-F. Chang, and S.-K. Lu, "Efficient double fault diagnosis for CMOS logic circuits", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.

111. S.-K. Lu, Y.-M. Chen, J.-L. Chen, and C.-W. Wu, "Logic diagnosis based on hardware emulator", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.

112. S.-K. Lu, T.-Y. Lee, and C.-W. Wu, "A Profit Evaluation System (PES) for Logic Cores at Early Design Stage", in Proc. 8th IEEE Int. Conf. on Electronics, Circuits and Systems, Malta, Sept. 2001, pp. 1491~1494.

113. Y.-F Chou, D.-M. Kwai, and C.-W. Wu, "Optimizing sensitivity of a latched sense amplifier for CMOS SRAM using a simulation-based method", in Proc. 9th Int. Symp. on Integrated Circuits, Devices & Systems (ISIC), Singapore, Sept. 2001.

114. J.-F Li, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "March-Based RAM Diagnosis Algorithms for Stuck-At and Coupling Faults", in Proc. IEEE Int. Test Conf. (ITC), Baltmore, Oct. 2001, pp. 758~767.

115. C.-W. Wang, R.-S. Tzeng, C.-F. Wu, C.-T. Huang, C.-W. Wu, S.-Y. Huang, S.-H. Lin, and H.-P. Wang, "A Built-In Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM ClustersA Built-In Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters", in Proc. 10th IEEE Asian Test Symp. (ATS), Kyoto, Nov. 2001, pp. 103~108.

116. K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, "Automatic Generation of Memory Built-In Self-Test Cores for System-on-Chip", in Proc. 10th IEEE Asian Test Symp. (ATS), Kyoto, Nov. 2001, pp. 91~96.

117. J.-C. Yeh, C.-F. Wu, K.-L. Cheng, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, "Flash Memory Built-In Self-Test Using March-Like Algorithms", in Proc. IEEE Int. Workshop on Electronic Design, Test, and Applications (DELTA), Christchurch, Jan. 2002, pp. 137~141.

118. J.-F. Li, H.-J. Huang, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I Chen, C.-Y. Hwang, and H.-P. Lin, "A Hierarchical Test Scheme for System-on-Chip Designs", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Paris, Mar. 2002, pp. 486~490.

119. C.-P. Su and C.-W. Wu, "Graph-based power-constrained test scheduling for SOC", in Proc. IEEE Int. Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Brno, Czech Republic, Apr. 2002, pp. 61~68 (Best Paper Award).

120. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, "Testing and Diagnosing Embedded Content Addressable Memories", in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, Apr. 2002, pp. 389~394.

121. K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu, "RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics", in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, Apr. 2002, pp. 281~286.

122. C.-W. Wang, J.-R. Huang, K.-L. Cheng, H.-S. Hsu, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "A test access control and test integration system for system-on-chip", in 6th IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), Monterey, California, May 2002, pp. P2.1~P2.8.

123. R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, "A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Isle of Bendor, France, July 2002, pp. 68~73.

124. T.-F. Lin, C.-P. Su, C.-T. Huang, and C.-W. Wu, "A High-Throughput Low-Cost AES Cipher Chip", in Proc. 3rd IEEE Asia-Pacific Conf. on ASIC, Taipei, Aug. 2002, pp. 85~88.

125. M.-C. Lee, J.-R. Huang, C.-P. Su, T.-Y. Chang, C.-T. Huang, and C.-W. Wu, "A true random generator design", in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 137~140.

126. Y.-C. Tsai, S.-Y. Huang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "Fine-grain mixed-level power estimation based on disparity path analysis", in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 199~202.

127. Y.-T. Lin, C.-P. Su, C.-T. Huang, C.-W. Wu, S.-Y. Huang, and T.-Y. Chang, "Low-power embedded memory architecture design for SOC", in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 306~309.

128. S.-K. Chiu, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, "Diagonal Test and Diagnostic Schemes for Flash Memories", in Proc. IEEE Int. Test Conf. (ITC), Baltmore, Oct. 2002, pp. 37~46.

129. C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "Test Scheduling of BISTed Memory Cores for SOC", in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 356~361.

130. H.-S. Hsu, J.-R. Huang, K.-L. Cheng, C.-W. Wang, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "Test Scheduling and Test Access Architecture Optimization for System-on-Chip", in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 411~416.

131. H.-C. Hong, J.-L. Huang, K.-T. Cheng, and C.-W. Wu, "On-chip Analog Response Extraction with 1-Bit Σ-∆ Modulators", in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 49~54.

132. M.-C. Sun, C.-P. Su, C.-T. Huang, and C.-W. Wu, "Design of a Scalable RSA and ECC Crypto-Processor", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Kitakyushu, Jan. 2003, pp. 495~498 (Best Paper Award).

133. C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, "A Highly Efficient AES Cipher Chip", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Kitakyushu, Jan. 2003, pp. 561~562 (Design Contest Special Feature Award).

134. C.-W. Wang, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "Test and Diagnosis of Word-Oriented Multiport Memories", in Proc. IEEE VLSI Test Symp. (VTS), Napa Valley, Apr. 2003, pp.248~253.

135. S.-K. Lu, J.-L. Chen, C.-W. Wu, W.-F. Chang, and S.-Y. Huang, "Combinational Circuit Fault Diagnosis Using Logic Emulation", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Bangkok, May 2003, vol. V, pp. 549~552.

136. R.-F. Huang, L.-M. Denq, and C.-W. Wu, "A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), San Jose, July 2003, pp. 53~56.

137. L.-M. Denq, R.-F. Huang, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, "A parallel built-in self-diagnosis scheme for embedded memory", in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 449~452.

138. H.-C. Liao, R.-F. Huang, J.-J. Liou, and C.-W. Wu, "An FPGA fault simulator for stuck-at and segment delay faults", in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 461~464.

139. S.-H. Shieh, C.-K. Tung, L.-R. Wu, and C.-W. Wu, "Low-power full adder core design for embedded structure", in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 221~224.

140. S.-H. Shieh and C.-W. Wu, "Carry-free adder design based on minimal redundant positive-digit number system", in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 257~260.

141. J.-H. Hong, C.-L. Liu, B.-Y. Tsai, and C.-W. Wu, "A radix-4 modular multiplier for fast RSA public-key cryptosystem", in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 553~556. 

142. C.-W. Wang, K.-L. Cheng, J.-N. Lee, Y.-F. Chou, C.-T. Huang, C.-W. Wu, F. Huang, and H.-T. Yang, "Fault Pattern Oriented Defect Diagnosis for Memories", in Proc. IEEE Int. Test Conf. (ITC), Charlotte, Sept. 2003, pp. 29~38.

143. J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, P.-Y. Tsai, A. Hsu, and E. Chow, "A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy", in Proc. IEEE Int. Test Conf. (ITC), Charlotte, Sept. 2003, pp. 393~402.

144. K.-L. Cheng, C.-W. Wang, J.-N. Lee, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, "FAME: A Fault-Pattern Based Memory Failure Analysis Framework", in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2003, pp. 595~598.

145. R.-F. Huang, Y.-F. Chou, and C.-W. Wu, "Defect Oriented Fault Analysis for SRAM", in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 256~261.

146. C.-L. Su, R.-F. Huang, and C.-W. Wu, "A Processor-Based Built-In Self-Repair Design for Embedded Memories", in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 366~371.

147. M.-Y. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "An HMAC Processor with Integrated SHA-1 and MD5 Algorithms", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2004, pp. 456~458.

148. R.-F. Huang, Y.-T. Lai, Y.-F. Chou, and C.-W. Wu, "SRAM Delay Fault Modeling and Test Algorithm Development", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP- DAC), Yokohama, Jan. 2004, pp. 104~109.

149. R.-F. Huang, C.-L. Su, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, "A Parallel Built-In Diagnostic Scheme for Multiple Embedded Memories", in Proc. IEEE Int. Workshop on Current & Defect Based Testing (DBT), Napa Valley, Apr. 2004, pp. 99~104.

150. L.-M. Denq, R.-F. Huang, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, "A Parallel Built-In Diagnostic Scheme for Multiple Embedded Memories", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), San Jose, Aug. 2004, pp. 65~69.

151. C.-H. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "A Word-Based RSA Crypto-Processor with Enhanced Pipeline Performance", in Proc. 4th IEEE Asia-Pacific Conf. on Advanced System Integrated Circuits (AP-ASIC), Fukuoka, Aug. 2004, pp. 218~221.

152. S.-F. Kuo, J.-C. Yeh, C.-W. Wu, and C.-H. Chen, "A systematic approach to semiconductor memory test time reduction", in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.

153. Y.-T. Lai, J.-C. Yeh, C.-W.Wu, and C.-H. Ho, "Flash memory built-in self-test with enhanced test mode control", in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.

154. S.-H. Shieh and C.-W. Wu, "A systematic approach to semiconductor memory test time reduction", in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.

155. Y.-T. Hsing, C.-W. Wang, C.-W. Wu, C.-T. Huang, and C.-W. Wu, "Failure Factor Based Yield Enhancement for SRAM Designs", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, Oct. 2004, pp. 20~28.

156. Y.-L. Peng, J.-J. Liou, C.-T. Huang, and C.-W. Wu, "An Application-Independent Delay Testing Methodology for Island-Style FPGA", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, Oct. 2004, pp. 478~486.

157. C.-L. Su, R.-F. Huang, C.-W. Wu, C.-C. Hung, M.-J. Kao, Y.-J. Chang, and W.-C. Wu, "MRAM Defect Analysis and Fault Modeling", in Proc. IEEE Int. Test Conf. (ITC), Charlotte, Oct. 2004, pp. 124~133.

158. K.-L. Cheng, J.-R. Huang, C.-W. Wang, C.-Y. Lo, L.-M. Denq, C.-T. Huang, C.-W. Wu, S.-W. Hung, and J.-Y. Lee, "An SOC Test Integration Platform and Its Industrial Realization", in Proc. IEEE Int. Test Conf. (ITC), Charlotte, Oct. 2004, pp. 1213~1222.

159. R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, and Y.-J. Chang, "Fail Pattern Identification for Memory Built-In Self-Repair", in Proc. 13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 366~371.

160. C.-T. Huang, J.-C. Yeh, Y.-Y. Shih, R.-F. Huang, and C.-W. Wu, "On Test and Diagnostics of Flash Memories", in Proc. 13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 260~265.

161. H.-C. Hong, C.-W. Wu, and K.-T. Cheng, "A Σ-∆ Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose", in Proc.13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 62~67.

162. C.-P. Su, C.-L. Horng, C.-T. Huang, and C.-W. Wu, "A Configurable AES Processor for Enhanced Security", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Shanghai, Jan. 2005, pp. 361~366.

163. C.-P. Su, C.-H. Wang, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "Design and Test of a Scalable Security Processor", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Shanghai, Jan. 2005, pp. 372~375.

164. C.-W. Wu, "SOC Testing Methodology and Practice", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Munich, Mar. 2005, pp. 1120~1121.

165. C.-L. Su, R.-F. Huang, C.-W. Wu, Y.-J. Chang, and S.-T. Lin, "Embedded Memory Diagnostic Data Compression Using  Differential Address", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications: Design, Automation and Test (VLSI-TSA-DAT), Hsinchu, Apr.2005, pp. 20~23.

166. H.-C. Liao, J.-J. Liou, Y.-L. Peng, C.-T. Huang, and C.-W. Wu, "Delay Defect Coverage for FPGA Test Configurations Based on Statistical Evaluation", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications: Design, Automation and Test (VLSI-TSA-DAT), Hsinchu, Apr. 2005, pp. 216~219.

167. J.-C. Yeh, Y.-T. Lai, Y.-Y. Shih, and C.-W. Wu, "Flash Memory Built-In Self-Diagnosis with Test Mode Control", in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs, May 2005, pp. 15~20.

168. C.-C. Wang, J.-J. Liou, Y.-L. Peng, C.-T. Huang, and C.-W. Wu, "A BIST Scheme for FPGA Interconnect Delay Faults", in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs, May 2005, pp. 201~206.

169. J.-C. Yeh, S.-F. Kuo, C.-W. Wu, C.-T. Huang, and C.-H. Chen, "A Systematic Approach to Reducing Semiconductor Memory Test Time in Mass Production", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Aug. 2005, pp. 97~102.

170. S.-M. Wang, C.-Y. Lo, C.-H. Wang, and C.-W. Wu, "Test integration of core-based system-on-chip supporting delay test", in Proc. 16th VLSI Design/CAD Symp., Hualien, Aug. 2005.

171. C.-K. Tung, S.-H. Shieh, M.-C. Tsai, and C.-W. Wu, "Novel hybrid full-swing full adder cores with output driving capability", in Proc. 16th VLSI Design/CAD Symp., Hualien, Aug. 2005.

172. C.-L. Su, Y.-T. Yeh, and C.-W. Wu, "An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Monterey, CA, Oct. 2005, pp. 81~89.

173. C.-H. Wang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, "Scalable Security Processor Design and Its Implementation", in Proc. IEEE Asian Solid-State Circuit Conf. (A-SSCC), Hsinchu, Nov. 2005, pp. 513~516.

174. Y.-C. Dawn, J.-C. Yeh, C.-W. Wu, C.-C. Wang, Y.-C. Lin, and C.-H. Chen, "Flash Memory Die Sort by a Sample Classification Method", in Proc. 14th IEEE Asian Test Symp. (ATS), Kolkatta, India, Dec. 2005, pp. 182~187.

175. C.-W. Wu, C.-T. Huang, S.-Y. Huang, P.-C. Huang, T.-Y. Chang, and Y.-T. Hsing, "The HOY Tester-Can IC Testing Go Wireless?", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2006, pp. 183~186.

176. P.-K. Chen, Y.-T. Hsing, and C.-W.Wu, "On Feasibility of HOY A Wireless Test Methodology for VLSI Chips and Wafers", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2006, pp. 243~246.

177. Y.-Y. Hsiao, C.-H. Chen, and C.-W. Wu, "A Built-In Self-Repair Scheme for NOR-Type Flash Memory", in Proc. IEEE VLSI Test Symp. (VTS), Berkeley, Apr. 2006, pp. 114~119.

178. C.-H. Wang, C.-Y. Lo, M.-S. Lee, J.-C. Yeh, C.-T. Huang, C.-W. Wu, and S.-Y. Huang, "A Network Security Processor Design Based on an Integrated SOC Design and Test Platform", in Proc. IEEE/ACM Design Automation Conf. (DAC), San Francisco, July 2006.

179. M.-H. Hsu, Y.-T. Hsing, J.-C. Yeh, and C.-W. Wu, "Fault-Pattern Oriented Defect Diagnosis for Flash Memory", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Aug. 2006, pp. 3~8.

180. C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, and M.-J. Kao, "Testing MRAM for Write Disturbance Fault", in Proc. IEEE Int. Test Conf. (ITC), Santa Clara, Oct. 2006.

181. B.-Y. Chen, Y.-T. Yeh, C.-H. Chen, J.-C. Yeh, C.-W. Wu, J.-S. Lee, and Y.-C. Lin, "An Enhanced EDAC Methodology for Low Power PSRAM", in Proc. IEEE Int. Test Conf. (ITC), Santa Clara, Oct. 2006.

182. L.-M. Denq, T.-C. Wang, and C.-W. Wu, "An Enhanced SRAM BISR Design with Reduced Timing Penalty", in Proc. 15th IEEE Asian Test Symp. (ATS), Fukuoka, Japan, Nov. 2006, pp. 25~30.

183. T.-W. Ko, Y.-T. Hsing, C.-W. Wu, and C.-T. Huang, "Stable Performance MAC Protocol for HOY Wireless Tester under Large Population", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2007, pp. 160~163.

184. Y.-T. Hsing, C.-C. Huang, J.-C. Yeh, and C.-W. Wu, "SDRAM Delay Fault Modeling and Performance Testing", in Proc. 25th IEEE VLSI Test Symp. (VTS), Berkeley, May 2007, pp. 53~58.

185. M.-S. Lee, L.-M. Denq, and C.-W. Wu, “BRAINS+: A Memory Built-in Self-Repair Generator”, in Proc. 1st VLSI Test Technology Workshop (VTTW), Hsinchu, July 2007.

186. W.-Y. Lo, C.-Y. Chen, C.-L. Su, and C.-W. Wu, "Testing MRAM for write disturbance fault", in Proc. 18th VLSI Design/CAD Symp., Hualien, Aug. 2007 (Best Paper Award).

187. Y.-T. Hsing, S.-G. Wu, and C.-W. Wu, “RAMSES-D: DRAM Fault Simulator Supporting Weighted Coupling Fault”, in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Dec. 2007, pp. 33~38.

188. C.-W. Wu, “How Far can We Go in Wireless Testing of Memory Chips and Wafers?”, in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Dec. 2007, pp. 31~32.

189. J.-J. Liou, C.-T. Huang, C.-W. Wu, C.-C. Tien, C.-H. Wang, H.-P. Ma, Y.-Y. Chen, Y.-C. Hsu, L.-M. Deng, C.-J. Chiu, Y.-W. Li, and C.-M. Chang, “A PROTOTYPE OF A WIRELESS-BASE TEST SYSTEM”, in Proc. IEEE Int. SOC Conf. (SOCC), Sept. 2007, pp. 225~228.

190. C.-L. Su, C.-W. Tsai, C.-W. Wu, J.-J. Chen, W.-C. Wu, C.-C. Hung, and M.-J. Kao, "Diagnosis for MRAM Write Disturbance Fault", in Proc. IEEE Int. Test Conf. (ITC), Santa Clara, Oct. 2007, pp. 1-9.

191. L.-M. Denq and C.-W. Wu, “A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories”, in Proc. 16th IEEE Asian Test Symp. (ATS), Beijing, Oct. 2007 , pp. 349~354.

192. H.-H. Wu, J.-F. Li, C.-F. Wu, and C.-W. Wu, “CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs”, in Proc. 16th IEEE Asian Test Symp. (ATS), Beijing, Oct. 2007, pp. 355~360.

193. Y.-T. Hsing, S.-G. Wu, and C.-W. Wu, “RAMSES-D: DRAM Fault Simulator Supporting Weighted Coupling Fault”, in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Dec. 2007, pp. 33~38.

194. C.-H. Lin, M.-S. Lee, C.-L. Su, and C.-W. Wu, “Evaluation of Redundancy Analysis Schemes for Reparable Memories with Redundancy Constraints”, in Proc. 2nd VLSI Test Technology Workshop (VTTW), Tainan, July 2008.

195. W.-Y. Lo, C.-Y. Chen, C.-L. Su, and C.-W. Wu, "Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault", in Proc. 17th IEEE Asian Test Symp. (ATS), Sapporo, Japan, Nov. 2008, pp. 417~422.

196. C.-K. Hsu, L.-M. Denq, M.-Y. Wang, J.-J. Liou, C.-T. Huang, and C.-W. Wu, "Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques", in Proc. 17th IEEE Asian Test Symp. (ATS), Sapporo, Japan, Nov. 2008, pp. 245~250.

197. C.-W. Tzeng, C.-Y. Lin, S.-Y. Huang, C.-T. Huang, J.-J. Liou, H.-P. Ma, P.-C. Huang, and C.-W. Wu, "iScan: Indirect-Access Scan Test over HOY Test Platform", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2009, pp. 60~63.

198. T.-H. Chen, Y.-Y. Hsiao, Y.-T. Hsing, and C.-W. Wu, “An Adaptive-Rate Error Correction Scheme for NAND Flash Memory”, in Proc. 27th IEEE VLSI Test Symp. (VTS), Santa Cruz, May 2009, pp. 53~58.

199. Y.-L. Peng and C.-W. Wu, “Testing for 3D FPGA interconnect open and short faults”, in Proc. 3rd VLSI Test Technology Workshop (VTTW), Nantou, July 2009.

200. Y.-F. Chou, D.-M. Kwai, and C.-W. Wu, “Memory Repair by Die Stacking with Through Silicon Vias”, in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2009, pp. 53~58.

201. C.-C. Chi, C.-Y. Lo, T.-W. Ko, and C.-W. Wu, “Test Integration for SOC Supporting Very Low-Cost Testers”, in Proc. 18th IEEE Asian Test Symp. (ATS), Taichung, Nov. 2009, pp. 287~292.

202. P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification”, in Proc. 18th IEEE Asian Test Symp. (ATS), Taichung, Nov. 2009, pp. 450~455.

203. J.-F. Li and C.-W. Wu, “Is 3D Integration an Opportunity or Just a Hype?” in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Taipei, Jan. 2010, pp. 541~543.

204. C.-Y. Chen and C.-W. Wu, "An Adaptive Code Rate EDAC Scheme for Random Access Memory", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Dresden, Mar. 2010, pp. 735~740.

205. P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “On-Chip Testing of Blind and Open-Sleeve TSVs for 3D IC before Bonding”, in Proc. 28th IEEE VLSI Test Symp. (VTS), Santa Cruz, Apr. 2010, pp. 263~268.

206. T.-Y. Wu, P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, "Improving Testing and Diagnosis Efficiency for Regular Memory Arrays", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2010, pp. 100~103.

207. C.-C. Chi, C.-W. Wu, and J.-F. Li, “A Low-Cost and Scalable Test Architecture for Multi-Core Chips”, in Proc. IEEE European Test Symp. (ETS), May 2010, pp. 30~35.

208. S.-H. Wang, C.-Y. Chen, and C.-W. Wu, "Fast Identification of Operating Current for Toggle MRAM by Spiral Search", in Proc. IEEE/ACM Design Automation Conf. (DAC), Anaheim, June 2010, pp. 923~928.

209. H.-M. Chang, J.-L. Huang, D.-M. Kwai, K.-T. Tim Cheng, and C.-W. Wu, "An Error Tolerance Scheme for 3D CMOS Imagers", in Proc. IEEE/ACM Design Automation Conf. (DAC), Anaheim, June 2010, pp. 917~922.

210. C.-W. Wu and J.-J. Tang, “Is automotive electronics creating new opportunities for semiconductor?” in Proc. 16th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Taipei, Oct. 2010.

211. T.-Y. Lee, S.-Y. Huang, H.-J. Hsu, C.-W. Tzeng, C.-T. Huang, J.-J. Liu, H.-P. Ma, P.-C. Huang, J.-C. Bor, C.-W. Wu, C.-C. Tien, M. Wang, "AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects", in Proc. IEEE 25th Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2010, pp. 340~348.

212. D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “Is 3D Integration the Way out of the Crossroads?” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Beijing, Nov. 2010, pp. 1~4.

213. J.-W. You, S.-Y. Huang, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “Performance Characterization of TSV in 3D IC via Sensitivity Analysis”, in Proc. 19th IEEE Asian Test Symp. (ATS), Shanghai, Dec. 2010, pp. 389~394.

214. C.-W. Chou, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Test Integration Methodology for 3D Integrated Circuits”, in Proc. 19th IEEE Asian Test Symp. (ATS), Shanghai, Dec. 2010, pp. 377~382.

215. X.-L. Huang, P.-Y. Kang, H.-M. Chang, J.-L. Huang, Y.-F. Chou, Y.-P. Lee, D.-M. Kwai, and C.-W. Wu, “A Self-Testing and Calibration Method for Embedded Successive Approximation Register ADC”, in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Japan, Jan. 2011, pp. 713-718.

216. H.-C. Shih, C.-Y. Chen, C.-W. Wu, C.-H. Lin, and S.-S. Sheu, “Training-Based Forming Process for RRAM Yield Improvement”, in Proc. 28th IEEE VLSI Test Symp. (VTS), Dana Point, May 2011, pp. 146~151.

217. Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Built-In Self-Test Scheme for the Post-Bond Test of TSV s in 3D ICs”, in Proc. 28th IEEE VLSI Test Symp. (VTS), Dana Point, May 2011, pp. 20~25.

218. C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “DfT Architecture for 3D-SICs with Multiple Towers”, in Proc. 16th IEEE European Test Symp. (ETS), Trondheim, Norway, May 2011, pp. 51-56.

219. C.-F. Li, C.-Y. Lee, C.-H. Wang, S.-L. Chang, Y.-S. Kuo, L.-M. Denq, C.-C. Chi, T.-Y. Chang, H.-J. Hsu, M.-Y. Chu, C.-T. Huang, J.-J. Liou, S.-Y. Huang, P.-C. Huang, H.-P. Ma, J.-C. Bor, C.-C. Tien, C.-H. Wang, and C.-W. Wu, “A Low-Cost Wireless Interface with No External Antenna and Crystal Oscillator for Cm-Range Contactless Testing”, in Proc. IEEE/ACM Design Automation Conf. (DAC), San Diego, USA, June 2011, pp. 771-776.

220. C.-Y. Chen, H.-C. Shih, M. Lee, C.-W. Wu, C.-H. Lin, and S.-S. Sheu, “Built-in self-forming, built-in self-test, and built-in self-repair for RRAM yield improvement”, in Proc. VLSI Test Tech. Workshop (VTTW), Nantou, July 2011.

221. C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “Post-Bond Testing of 2.5D-SICs and 3D-SICs Containing a Passive Silicon Interposer Base”, in Proc. IEEE Int. Test Conf. (ITC), Anaheim, USA, Sept. 2011, Paper 17.3.

222. C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “Multi-Visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base”, in Proc. 20th IEEE Asian Test Symp. (ATS), New Delhi, India, Nov. 2011, pp. 451-456.

223. C.-W. Wu, S.-K. Lu, and J.-F. Li, “On Test and Repair of 3D Random Access Memory”, in Proc. 17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, Jan. 2012, pp. 744-749.

224. [224] B.-Y. Lin, M. Lee and C.-W. Wu, “A Memory Failure Pattern Analyzer for Memory Diagnosis and Repair”, in Proc. 29th IEEE VLSI Test Symp. (VTS), Maui, Hawaii, Apr. 2012, pp. 234-239.

225. Y.-W. Chou, P.-Y. Chen, M. Lee, and C.-W. Wu, “Cost Modeling and Analysis for Interposer-Based Three-Dimensional IC”, in Proc. 29th IEEE VLSI Test Symp. (VTS), Maui, Hawaii, Apr. 2012, pp. 108-113.

226. C.-C. Chi, Y.-F. Chou. D.-M. Kwai, Y.-Y. Hsiao, C.-W. Wu, Y.-T. Hsing, L.-M. Denq, and T.-H. Lin, “3D-IC BISR for Stacked Memories Using Cross-Die Spares”, in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2012, pp. 1-4.

227. T.-H. Wu, P.-Y. Chen, M. Lee, B.-Y. Lin, C.-W. Wu, C.-H. Tien, H.-C. Lin, H. Chen, C.-N. Peng, and M.-J. Wang, “A Memory Yield Improvement Scheme Combining Built-In Self-Repair and Error Correction Codes”, in Proc. IEEE Int. Test Conf. (ITC), Anaheim, CA, Nov. 2012, Paper 14.1.

228. Y.-C. Yu, J.-F. Li, C.-W. Chou, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A Built-In Self-Test Scheme for 3D RAMs”, in Proc. IEEE Int. Test Conf. (ITC), Anaheim, CA, Nov. 2012, Paper 14.4.

229. S.-S. Chen, C.-K. Hsu, H.-C. Shih, J.-C. Yeh, C.-W. Wu, “Processor and DRAM Integration by TSV-Based 3-D Stacking for Power-Aware SOCs”, in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2013.

230. H.-C. Shih, and C.-W. Wu, "An Enhanced Double-TSV Scheme for Defect Tolerance in 3D-IC", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Grenoble, Mar. 2013.

231. Y. Shiyanovskii, C. Papachristou, and C.-W. Wu, “Analytical Modeling and Numerical Simulations of Temperature Field in TSV-based 3D ICs”, in Proc. 14th Int. Symp. on Quality Electronic Design (ISQED), Santa Clara, CA, Mar. 2013.

232. C.-C. Chi, C.-W. Wu, M.-J. Wang, and H.-C. Lin, “3D-IC Interconnect Test, Diagnosis, and Repair”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013.

233. C.-S. Hou, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou , and C.-W. Wu “An FPGA-Based Test Platform for Analyzing Data  Retention Time Distribution of DRAMs”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013.

234. Y.-C. Yu, C.-S. Hou, L.-J. Chang, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu “A Hybrid ECC and Redundancy Technique for Reducing Refresh Power of DRAMs”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013.

235. B.-Y. Lin, M. Lee, C.-W. Wu, "Failure-Pattern-Based Test Data Compression for Memories", in Proc. VLSI Test Technology Workshop (VTTW), New Taipei City, Jul. 2013.

236. B.-Y. Lin, M. Lee, and C.-W. Wu, "Exploration Methodology for 3D Memory Redun- dancy Architectures under Redundancy Constraints", in Proc. 22nd IEEE Asian Test Symp. (ATS), Yilan, Nov. 2013.

237. B.-Y. Lin, W.-T. Chiang, C.-W. Wu, M. Lee, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Redundancy Architectures for Channel-Based 3D DRAM Yield Improvement”, in Proc. IEEE Int. Test Conf. (ITC), Seattle, Washington, Oct. 2014.

238. Y.-C. Yu, C.-C. Yang, J.-F. Li, C.-Y. Lo, C.-H. Chen, J.-S. Lai, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs", in Proc. 23rd IEEE Asian Test Symp. (ATS), Hangzhou, Nov. 2014.

239. B.-Y. Lin, C.-W. Wu, and H. H. Chen, “System-Level Test Coverage Prediction by Structural Stress Test Data Mining”, in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2015.

240. P.-W. Luo, C.-K. Chen, Y.-H. Sung, W. Wu, H.-C. Shih, C.-H. Lee, K.-H. Lee, M.-W. Li, M.-C. Lung, C.-N. Lu, Y.-F. Chou, P.-L. Shih, C.-H. Ke, C. Shiah, P. Stolt, S. Tomishima, D.-M. Kwai, B.-D. Rong, N. Lu, S.-L. Lu, and C.-W. Wu, “A Computer Designed Half Gb 16-Channel 819Gb/s High-Bandwidth and 10ns Low-Latency DRAM for 3D Stacked Memory Devices Using TSVs”, in Proc. IEEE Symp. VLSI Circuits (VLSI), June 2015.

241. S.-Y. Wei, B.-Y. Lin, and C.-W. Wu, “A Fast Sweep-Line-Based Failure Pattern Extractor for Memory Diagnosis”, in Proc. IEEE Eropean Test Symposium (ETS), Amsterdam, May 2016.

242. Y.-C. Huang, B.-Y. Lin, C.-W. Wu, M. Lee, H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Efficient Probing Schemes for Fine-Pitch Pads of InFO Wafer-Level Chip-Scale Package”, in Proc. IEEE/ACM Design Automation Conf. (DAC), Austin, USA, June 2016.

243. H.-W. Liu and C.-W. Wu, "Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test", in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016.

244. C.-W. Wu, "Symbiotic-System Approach for IOT Devices", in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (Keynote in Honor of Prof. McCluskey).

245. H. H. Chen, S. Chen, P.-Y. Chuang, and C.-W. Wu, "Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation", in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (Best Paper Award).

246. K.-W. Hou and C.-W. Wu, "Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM", in Proc. VLSI Test Technology Workshop (VTTW), Nantou, Jul. 2017.

247. P.-Y. Chuang, C.-W. Wu, and H. H. Chen, “Cell-Aware Test Generation Time Reduction by Using Switch-Level ATPG”, in Proc. IEEE Int. Test Conf. in Asia (ITC-A), Taipei, Sept. 2017.

248. C.-W. Wu, B.-Y. Lin, H.-W. Hung, S.-M. Tseng, and C. Chen, “Symbiotic System Models for Efficient IOT System Design and Test”, in Proc. IEEE Int. Test Conf. in Asia (ITC-A), Taipei, Sept. 2017.

249. B.-Y. Lin, H.-W. Hung, S.-M. Tseng, C. Chen, and C.-W. Wu, “Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems”, in Proc. IEEE Int. Test Conf. (ITC), Fort Worth, Texas, Oct. 2017. (Invited Presentation)

250. P.-M. P. Law, C.-W. Wu, L.-Y. Lin, H.-C. Hong, H. Chen, H.-C. Lin, and M.-J. Wang, "An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages", in Proc. 26th IEEE Asian Test Symp. (ATS), Taipei, Nov. 2017.

251. P.-Y. Chuang, C.-W. Wu, and H. H. Chen, “Covering Hard-to-Detect Defects by Thermal Quorum Sensing”, in Proc. IEEE Int. European Test Symposium (ETS), Bremen, May. 2018.

252. Y.-R. Jian, F. Fodor, E. J. Marinissen, and C.-W. Wu, “Automated Probe-Mark Analysis”, in Proc. Semiconductor Wafer Test Workshop (SWTW), San Diego, Jun. 2018.

253. S.-F. Kuo and C.-W. Wu, “Symbiotic Controller Design Using a Memory-Based FSM Model”, in Proc. 27th IEEE Int. Symp. Industrial Electronics (ISIE), Cairns, Jun. 2018.

254. Y.-C. Pan, Y.-R. Jian, H.-H. Liu, and C.-W. Wu, "A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices", in Proc. VLSI Test Technology Workshop (VTTW), Nantou, Jul. 2018.

255. J.-Y. Hu and C.-W. Wu, “RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction”, in Proc. IEEE Int. Test Conf. in Asia (ITC-A), Harbin, Aug. 2018.

256. M.-C. Chen, T.-H. Wu, and C.-W. Wu, “A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit”, in Proc. 27th IEEE Asian Test Symposium (ATS), Hefei, Oct. 2018 (Best Paper Award).

257. Y.-C. Kao, and C.-W. Wu, “A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning”, in Proc. Asilomar Conf. Signals, Systems, and Computers, Pacific Grove, CA, Oct. 2018.

258. E. J. Marinissen, F. Fodor, A. Podpod, M. Stucchi, Y.-R. Jian, and C.-W. Wu, “Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits”, in Proc. IEEE Int. Test Conf. (ITC), Phoenix, Arizona, Oct. 2018.

259. M. Inoue, X. Li, C.-W. Wu, “Asian Test Symposium - Past, Present and Future”, in Proc. IEEE Int. Test Conf. (ITC), Washington, DC, Nov. 2019.

260. M.-C. Hu, Z. Gao, S. Malagi, J. Swenton, J. Huisken, K. Goossens, C.-W. Wu, and E. J. Marinissen,  “Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults”, in Proc. IEEE European Test Symposium (ETS), Tallinn, Estonia, May 2020 (Best Paper Finalist).

261. P.-Y. Chuang, P.-Y. Tan, C.-W. Wu, and J.-M. Lu, “A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification”, in Proc. IEEE/ACM Design Automation Conf. (DAC), San Francisco, CA, July 2020.

262. C.-H. Chuang, K.-W. Hou, C.-W. Wu, M. Lee, C.-H. Tsai, H. Chen, and M.-J. Wang, “Improving the Quality and Reliability of Integrated Passive Devices with Deep Learning”, in Proc. VLSI Test Technology Workshop (VTTW), Kaohsiung, July. 2020 (Best Paper Award).

263. C.-T. King, J.-Y. Chang, C.-W. Wu, J.-J. Liou, C.-T. Huang, "AI Chip Development Environment Based on Human Skill Transfer and Its Application to Humanoid Two-Handed Robots", in Proc. 31st VLSI Design/CAD Symp., Taichung, Aug. 2020.

264. P.-Y. Chuang, P.-Y. Tan, C.-W. Wu, and J.-M. Lu, "A Low-Power Spiking Neural Network Chip for Image Classification", in Proc. 31st VLSI Design/CAD Symp., Taichung, Aug. 2020.

265. C.-H. Chuang, K.-W. Hou, C.-W. Wu, M. Lee, C.-H. Tsai, H. Chen, and M.-J. Wang, “A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices”, in Proc. IEEE Int. Test Conf. in Asia (ITC-A), Taipei, Sept. 2020 (Best Paper Award, invited presentation at ITC20).

266. C.-H. Chuang, K.-W. Hou, C.-W. Wu, M. Lee, C.-H. Tsai, H. Chen, and M.-J. Wang, “A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices”, in Proc. IEEE Int. Test Conf. (ITC), Washington, DC, Nov. 2020 (Invited presentation from ITC-A20 with extended content).

267. P.-Y. Tan, C.-W. Wu, and J.-M. Lu, “An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks”, in Proc. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021, pp. 575-580, doi: 10.23919/DATE51398.2021.9474151.

268. J.-Y. Fang, P.-Y. Chuang, C.-W. Wu, and H. H. Cheng, “Improving the Quality of Semiconductor Products with Enhanced Decision Tree and Random Forest”, in Proc. VLSI Test Technology Workshop (VTTW), Kaohsiung, July 2021.

269. C.-H. Tung, P.-Y. Tan, and C.-W. Wu, "A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array", in Proc. 32nd VLSI Design/CAD Symp., Pingtung, Aug. 2021.

270. H.-H. Cheng, K.-W. Hou, and C.-W. Wu, "Fault Models and Test Algorithms for Memristor-Based Spiking Neural Network", in Proc. 32nd VLSI Design/CAD Symp., Pingtung, Aug. 2021.

271. P.-Y. Tan, C.-H. Tung, C.-W. Wu, M. Lee, and G. Liao, "A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2022.

272. H.-H. Wang, P.-Y. Chuang, and C.-W. Wu, "A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2022.

273. S.-Y. Lin, P.-Y. Tan, C.-W. Wu, M.-D. Shieh, C.-H. Chuang, and G. Liao, "Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability", in Proc. IEEE Int. Test Conf. in Asia (ITC-Asia), Taipei, Aug. 2022.

274. Y.-C. Cheng, P.-Y. Tan, C.-W. Wu, M.-D. Shieh, C.-H. Chuang, and G. Liao, "A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips", in Proc. IEEE Int. Test Conf. in Asia (ITC-Asia), Taipei, Aug. 2022 (Best Paper Award finalist, invited presentation at ITC22).

275. K.-W. Hou, H.-H. Cheng, C. Tung, C.-W. Wu, and J.-M. Lu, “Fault Modeling and Testing of Memristor-Based Spiking Neural Networks”, in Proc. IEEE Int. Test Conf. (ITC), Anaheim, CA, Sept. 2022. 

276. Y.-C. Cheng, P.-Y. Tan, C.-W. Wu, M.-D. Shieh, C.-H. Chuang, and G. Liao, "Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method", in Proc. IEEE Int. Test Conf. (ITC), Anaheim, CA, Sept. 2022 (Invited presentation from ITC-A22 with extended content). 

277. Y.-Y. Chou, C.-W. Wu, M.-D. Shieh, and C.-H. Chen, “Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration”, in Proc. 31st IEEE Asian Test Symposium (ATS), Taichung, Nov. 2022. 

278. K.-H. Duh, C.-W. Wu, M.-D. Shieh, C.-H. Chen, and M.-Y. Fan, “Aging Impact of Power MOSFETs in Charger with Different Operation Frequency”, in Proc. 31st IEEE Asian Test Symposium (ATS), Taichung, Nov. 2022. 

279. P.-Y. Tan and C.-W. Wu, "A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks", in Proc. 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Jan. 2023.

280. C. Tung, K.-W. Hou, and C.-W. Wu, “A Built-In Self-Calibration Scheme for Memristor-Based Spiking Neural Network”, in Proc. Int. VLSI Symp. Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), Apr. 2023 (Best Paper Award finalist).

281. P.-Y. Chuang, F. Lorenzelli, S. Chakravarty, C.-W. Wu, G. Gielen, and E. J. Marinissen, “Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages”, in Proc. IEEE 41st VLSI Test Symp. (VTS), Apr. 2023.

282. P.-Y. Chuang, F. Lorenzelli, S. Chakravarty, S. Boutobza, C.-W. Wu, G. Gielen, and E. J. Marinissen, “Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Package”, in Proc. IEEE Int. 3D Systems Integration Conference (3DIC), May 2023.

OTHER PUBLICATIONS

[1] C.-W. Wu, "Design of testable iterative logic arrays for DCT", NSC Engineering Science & Technology Newsletter, no. 13, pp. 64~66, Dec. 1995 (in Chinese).

[2] C.-W.Wu, "Advanced VLSI chip design", NSC Engineering Science & Technology Newsletter, no. 19, pp. 40~42, Sept. 1996, (in Chinese).

[3] C.-W. Wu, "ATS 96 meets in Taiwan", IEEE Design & Test of Computers, vol. 14, no. 1, pp. 88~89, Jan.-Mar. 1997.

[4] C.-W. Wu, "Should we worry about pennies for power?", Test Technology Newsletter, IEEE Computer Society, pp. 3~4, July-Aug. 1997.

[5] C.-W. Wu, "VLSI design and design technology development for a low power wireless transceiver", NSC Engineering Science & Technology Bulletin, no. 34, pp. 35~37, Dec. 1998 (in Chinese).

[6] C.-W. Wu, "Pioneers of SOC design: NTHU IC Design Technology Center", IC Design Magazine, vol. 9, pp. 56~64, Dec. 2000 (in Chinese).

[7] C.-T. Huang and C.-W. Wu, "Overview of memory testing technology", IC Design Magazine, vol. 9, pp. 72~76, Dec. 2000 (in Chinese).

[8] C.-W. Wu, C.-H. Wu, and Y.-L. Lin, "Communications IP: Development of a low-power communications processor core", NSC Engineering Science & Technology Bulletin, no. 54, pp. 9~14, Dec. 2000 (in Chinese).

[9] C.-W. Wu, K.-J. Lee, and Y.-L. Lin, "Foreword for the Special Issue on VLSI Testing", Jour. of Inform. Science and Engineering, vol. 16, no. 5, Sept. 2000.

[10] C.-W. Wu and C.-T. Huang, "VLSI Test Technology Forum", IC Design Magazine, vol. 12, pp. 86~88, Mar. 2001 (in Chinese).

[11] C.-W. Wu, "Foreword for the Special Issue on Design and Test of System-on-Chip", Jour. of Chinese Institute of Electrical Engineering, vol. 8, no. 4, Nov. 2001.

[12] C.-W. Wu and C.-T. Huang, "Communications IP: Instruction set architecture, functional units, and test circuitry of a communications processor core", NSC Engineering Science & Technology Bulletin, no. 58, pp. 139~143, Oct. 2001 (in Chinese).

[13] C.-W. Wu, C.-T. Huang, and C.-Y. Wu, "2001 International Workshop on IC-SOC", IEEE Circuits and Systems Magazine, vol. 1, no. 4, pp. 45~46, 4th Quarter 2001.

[14] C.-W. Wang, C.-F. Wu, J.-F. Li, R.-F. Huang, and C.-W. Wu, "SRAM built-in self-test and built-in self-diagnosis", IC Design Magazine, vol. 32, pp. 46~62, Dec. 2002 (Chinese translation and extension of our ATS'00 paper).

[15] C.-P. Su, M.-Y. Wang, and C.-W. Wu, "Introduction to crypto-processor", CIEE Magazine, pp. 40-49, Sept. 2003 (in Chinese).

[16] C.-W. Wu, "The high-tech nomadic", IC Design Magazine, vol. 44, pp. 76~82, Dec. 2003 (in Chinese).

[17] K. Hatayama, R. Rajsuman, C.-W. Wu, Y. Nishimura, S. Chakradhar, A. Merschon, D. Petrich, and T. Tada, "Opportunities with the open architecture test system", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2004, pp. 334~334, Panel Discussion.

[18] C.-W. Wu, "What has SOC to do with you?", National Chi Nan University Electronic Magazine, no. 30, June 2005 (in Chinese).

[19] C.-W. Wu, "An OEM family", Components Times Magazine, no. 186, Apr. 2007 (in Chinese).

[20] C.-W. Wu and M.-S. Lee, "Memory yield and reliability enhancement methodology for nano-scale SOC", NSC Engineering Science & Technology Bulletin, no. 104, p. 69, Feb. 2010 (in Chinese).

[21] C.-W. Wu, D. Dunning, F. Chen, and H.-H. Lee, "Design and Test of 3D and Emerging Memories", in Proc. 28th IEEE VLSI Test Symp. (VTS), Dana Point, May 2011, p. 328, May 2011 (Special Session: Hot Topic).

[22] J.-F. Li, C.-W. Wu, M. Aoyagi, M.-F. Chang, and D.-M. Kwai, “3D-IC Design and Test”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013 (Special Session 4C: Hot Topic).

[23] C.-W. Wu, "Holistic Approach to Low-Power System Design", in Proc. IEEE Int. Symp. on Low Power Electronics and Design (ISLPED), Beijing, Sept. 4-6, 2013 (Keynote Speech).

[24] B.-Y. Lin and C.-W. Wu, “Redundancy Architectures and Analysis Methodologies for 3D Memories Yield Improvement”, in Proc. IEEE Int. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Seattle, Washington, Oct. 2014 (Special Session: Ongoing PhD Research in 3D-Test).

[25] C.-W. Wu, "Is IOT Coming to the Rescue of Semiconductor?", in Proc. 21st IEEE European Test Symp. (ETS), Amsterdam, May 2016 (Keynote Speech).

[26] C.-W. Wu, "Symbiotic-System Approach for IOT Devices", in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (McCluskey Keynote Speech).

[27] C.-W. Wu, H. Fujiwara, X. Li, K.-J. Lee, and S. Kajihara "25th Anniversary Panel Session: Past, Present, and Future of ATS", in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (Panel Discussion Session).

[28] C.-W. Wu, “Can IOT make semiconductor great again?”, in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2017.

[29] K.-W. Hou and C.-W. Wu, "The Fate of IOT Relies on AI and Semiconductor", CIEE Magazine, Sept. 2017 (in Chinese).

[30] J.-M. Lu and C.-W. Wu, "Strengthening AI Chip R&D and Inter-Disciplinary Integration of Systems and Applications for Business Opportunities in the New Era", Jour. Infor. and Comm. Technology, ITRI, Feb. 2020 (https://ictjournal.itri.org.tw/content/Messagess/contents.aspx?PView=1&SiteID=654246032665636316&MmmID=654304432122064271&SSize=10&MSID=1037365742323163355) (in Chinese). 

[31] C.-W. Wu, M.-D. Shieh, J.-J. Lien, J.-F. Yang, W.-T. Chu, T.-H. Huang, H.-C. Hsieh, H.-T. Chiu. K.-C. Tu, Y.-T. Chen, S.-Y. Lin, J.-J. Hu, C.-H. Lin, and C.-S. Jheng, “Enhancing Fan Engagement in a 5G Stadium with AI-Based Technologies and Live Streaming”, TechRxiv, Preprint, https://doi.org/10.36227/techrxiv.16547397.v1, Sept. 2021.

[32] C.-W. Wu, "Sport Culture and Sport Technology Vitalizes Innovative Sport Industry", National Sports Quarterly, no. 211, Sept. 2022 (in Chinese).