Course Description
Advanced course for VLSI Testing and Design for Testability (DFT), with emphasis on semiconductor memory testing, diagnosis, and repair
Students expected to learn basic theory, methodologies, and software & hardware architectures, and to pick up hands on experiences through homework and term project
Recommended: EE6250 VLSI Testing (or equivalent)
Required: Familiarity with integrated circuits
Required: C/C++/Python and Verilog
Textbook
L. T. Wang, C. W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures, Elsevier (Morgan Kaufmann), San Francisco, 2006
References
Ad J. van de Goor , Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester , England, 1991
Technical papers
Course Outline
Introduction and review of IC testing
RAM functional fault models
RAM test algorithms
RAM fault coverage analysis
Testing word oriented and multi port memories
Memory built in self test (BIST)
Memory built in self diagnosis (BISD)
Memory redundancy repair
Memory built in self repair (BISR)
RAM on line testing
Memory failure analysis
Flash memory testing
Advanced topics (where time allows)
Emerging NVM test, 3D memory test, symbiotic/neuromorphic memory test, etc.