International Journals
D. Bakalis, X. Kavousianos, H. T. Vergos, D. Nikolos and G. Alexiou, "Low Power Built-In Self-Test Schemes for Array and Booth Multipliers", VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Gordon and Breach Publishers, vol. 12, no. 3, pp. 431-448, 2001.
E. Kalligeros, X. Kavousianos, D. Bakalis and D. Nikolos, "On-the-fly Reseeding: A New Reseeding Technique for test-per-clock BIST", Journal of Electronic Testing: Theory and Applications (JETTA), Kluwer Academic Publishers, vol. 18, no. 3, pp. 315-332, June 2002.
X. Kavousianos, D. Bakalis, D. Nikolos and S. Tragoudas, "A new Built-In TPG for Random Pattern Resistant Faults", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 21, no. 7, pp. 859-866, July 2002.
D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos and G. Alexiou, "On the Design of Low Power BIST for Multipliers with Booth Encoding and Wallace Tree Summation", Journal of Systems Architecture (JSA), Elsevier Science, vol. 48, no. 4-5, pp. 125-135, December 2002.
D. Bakalis, K. D. Adaos, D. Lymperopoulos, M. Bellos, H. T. Vergos, G. Ph. Alexiou and D. Nikolos, "A Core Generator for Arithmetic Cores and Testing Structures with a Network Interface", Journal of Systems Architecture (JSA), Elsevier Science, vol. 52, no. 1, pp. 1-12, January 2006.
D. Bakalis and H. T. Vergos, "Shifter Circuits for {2n+1, 2n, 2n-1} RNS", Electronics Letters (ELL), IET, vol. 45, no. 1, pp. 27-29, 1 January 2009.
X. Kavousianos, D. Bakalis and D. Nikolos, "Efficient Partial Scan Cell Gating for Low-Power Scan-based Testing", ACM Transactions on Design Automation of Electronic Systems (TODAES), ACM, vol. 14, no. 2, article no. 28, March 2009.
H. T. Vergos, D. Bakalis and C. Efstathiou, "Fast Modulo 2n+1 Multi-Operand Adders and Residue Generators", Integration, the VLSI Journal, Elsevier, vol. 43, no. 1, pp. 42-48, January 2010.
H. T. Vergos and D. Bakalis, "On Implementing Efficient Modulo 2n+1 Arithmetic Components", Journal of Circuits, Systems and Computers, World Scientific, vol. 19, no. 5, pp. 911-930, August 2010.
D. Bakalis, H. T. Vergos and A. Spyrou, "Efficient Modulo 2n±1 Squarers", Integration, the VLSI Journal, Elsevier, vol. 44, no. 3, pp. 163-174, June 2011.
E. Vassalos, D. Bakalis and H. T. Vergos, "On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors", Circuits, Systems and Signal Processing, Springer, vol. 30, no. 6, pp. 1445-1461, December 2011.
E. Vassalos and D. Bakalis, "CSD-RNS-based Single Constant Multipliers", Journal of Signal Processing Systems, Springer, vol. 67, no. 3, pp. 255-268, June 2012.
H. T. Vergos and D. Bakalis, "Area-Time Efficient Multi-Modulus Adders and their Applications", Microprocessors and Microsystems, Elsevier, vol. 36, no. 5, pp. 409-419, July 2012.
H. T. Vergos, D. Bakalis and A. Anastasiou, "Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators", Circuits, Systems and Signal Processing, Springer, vol. 34, no. 4, pp. 1041-1056, April 2015.
E. Vassalos and D. Bakalis, "Efficient architectures for modulo 2n-2 arithmetic units", International Journal of Electronics, Taylor & Francis, vol. 102, no. 12, pp. 2062-2074, December 2015.
Book Chapters
E. Vassalos, D. Bakalis and H. T. Vergos, "SUT-RNS Forward and Reverse Converters", VLSI 2010 Annual Symposium: Selected Papers, Lecture Notes in Electrical Engineering, vol. 105, chapter 14, pp. 231-244, Springer, 2011.
Conferences, Symposia and Workshops
D. Bakalis and D. Nikolos, "On Low Power BIST for Carry Save Array Multipliers", Proceedings of 5th IEEE International On-Line Testing Workshop (IOLTW), pp. 86-90, Rhodes, Greece, July 5-7, 1999.
D. Bakalis, H. T. Vergos, D. Nikolos, X. Kavousianos and G. Alexiou, "Low Power Dissipation in BIST Schemes for Modified Booth Multipliers", Proceedings of 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 121-129, Albuquerque, NM, USA, November 1-3, 1999.
D. Bakalis, E. Kalligeros, D. Nikolos, H. T. Vergos and G. Alexiou, "Low Power BIST for Wallace Tree-based Fast Multipliers", Proceedings of 1st IEEE International Symposium on Quality of Electronic Design (ISQED), pp. 433-438, San Jose, CA, USA, March 20-22, 2000.
D. Bakalis, D. Nikolos and X. Kavousianos, "Test Response Compaction by an Accumulator Behaving as a Multiple-Input Non-Linear Feedback Shift Register", Proceedings of International Test Conference (ITC), pp. 804-811, Atlantic City, NJ, USA, October 1-6, 2000.
D. Bakalis, M. Bellos, H. T. Vergos, D. Nikolos and G. Alexiou, "A Macro Generator for Arithmetic Cores", Proceedings of XV Conference on Design of Circuits and Integrated Systems (DCIS), pp. 734-739, Montpellier, France, November 21-24, 2000.
D. Bakalis, D. Nikolos, H. T. Vergos and X. Kavousianos, "On Accumulator-based Bit-Serial Test Response Compaction Schemes", Proceedings of 2nd IEEE International Symposium on Quality Electronic Design (ISQED), pp. 350-355, San Jose, CA, USA, March 26-28, 2001.
X. Kavousianos, D. Bakalis and D. Nikolos, "A Novel Reseeding Technique for Accumulator-based Test Pattern Generation", Proceedings of 11th ACM Great Lakes Symposium on VLSI (GLS_VLSI), pp. 7-12, West Lafayette, IN, USA, March 22-23, 2001.
D. Bakalis, K. D. Adaos, D. Lymperopoulos, G. Ph. Alexiou and D. Nikolos, "EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores", Proceedings of 12th IEEE International Workshop on Rapid System Prototyping (RSP), pp. 182-187, Monterey, CA, USA, June 25-27, 2001.
S. J. Piestrak, D. Bakalis and X. Kavousianos, "On the Design of Self-Testing Checkers for Berger codes", Proceedings of 7th IEEE International On-Line Testing Workshop (IOLTW), pp. 153-157, Taormina, Italy, July 9-11, 2001.
E. Kalligeros, X. Kavousianos, D. Bakalis and D. Nikolos, "A new Reseeding Technique for LFSR-based Test Pattern Generation", Proceedings of 7th IEEE International On-Line Testing Workshop (IOLTW), pp. 80-86, Taormina, Italy, July 9-11, 2001.
Ε. Kalligeros, X. Kavousianos, D. Bakalis and D. Nikolos, "An Efficient Seeds Selection Method for LFSR-based Test-per-clock BIST", Proceedings of 3rd IEEE International Symposium on Quality Electronic Design (ISQED), pp. 261-266, San Jose, CA, USA, March 18-20, 2002.
G. Dimitrakopoulos, D. Nikolos and D. Bakalis, "Bit Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register", Proceedings of 8th IEEE International On-Line Testing Workshop (IOLTW), pp. 152-157, Isle of Bendor, France, July 8-10, 2002.
X. Kavousianos, D. Bakalis, Μ. Bellos and D. Nikolos, "An Efficient Test Vector Ordering Method for Low Power Testing", Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 285-288, Louisiana, LA, USA, February 19-20, 2004.
M. Bellos, D. Bakalis and D. Nikolos, "Scan Cell Ordering for Low Power BIST", Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 281-284, Louisiana, LA, USA, February 19-20, 2004.
M. Bellos, D. Bakalis, D. Nikolos and X. Kavousianos, "Low Power Testing by Test Vector Ordering with Vector Repetition", Proceedings of IEEE International Symposium on Quality Electronic Design (ISQED), pp. 205-210, San Jose, CA, USA, March 22-24, 2004.
M. Bellos, D. Bakalis, D. Nikolos and X. Kavousianos, "Vector Repetition and Modification for Peak Power Reduction in VLSI Testing", Proceedings of 8th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS), pp. 160-165, Sopron, Hungary, April 13-16, 2005.
H. T. Vergos, D. Bakalis and C. Efstathiou, "Efficient Modulo 2n+1 Multi-Operand Adders", Proceedings of 15th IEEE International Conference on Electronics, Circuits & Systems (ICECS), pp. 694-697, Malta, August 31-September 3, 2008.
H. T. Vergos and D. Bakalis, "On the Use of Diminished-1 Adders for Weighted Modulo 2n+1 Arithmetic Components", Proceedings of 11th Euromicro Conference on Digital System Design: Architectures, Methods & Tools (DSD), pp. 752-759, Parma, Italy, September 3-5, 2008.
A. Spyrou, D. Bakalis and H. T. Vergos, "Efficient Architectures for Modulo 2n-1 Squarers", Proceedings of 16th International Conference on Digital Signal Processing (DSP), Santorini, Greece, July 5-7, 2009.
E. Vassalos, D. Bakalis and H. T. Vergos, "Novel Modulo 2n+1 Subtractors", Proceedings of 16th International Conference on Digital Signal Processing (DSP), Santorini, Greece, July 5-7, 2009.
E. Vassalos and D. Bakalis, "Combined SD-RNS Constant Multiplication", Proceedings of 12th Euromicro Conference on Digital System Design: Architectures, Methods & Tools (DSD), pp. 172-179, Patras, Greece, August 27-29, 2009.
E. Vassalos, D. Bakalis and H. T. Vergos, "SUT-RNS Forward and Reverse Converters", Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 11-16, Lixouri, Kefalonia, Greece, July 5-7, 2010.
D. Bakalis and H. T. Vergos, "Area-Efficient Multi-Moduli Squarers for RNS", Proceedings of 13th Euromicro Conference on Digital System Design: Architectures, Methods & Tools (DSD), pp. 408-411, Lille, France, September 1-3, 2010.
D. Bakalis and H. T. Vergos, "Diminished-One Modulo 2n+1 Multiply-Add Circuits", Proceedings of XXV Conference on Design of Circuits and Integrated Systems (DCIS), pp. 289-294, Canary Islands, Spain, November 17-19, 2010.
H. T. Vergos and D. Bakalis, "Area-Time Efficient Multi-Moduli Adder Design", Proceedings of XXV Conference on Design of Circuits and Integrated Systems (DCIS), pp. 295-300, Canary Islands, Spain, November 17-19, 2010.
E. Vassalos, D. Bakalis and H. T. Vergos, "On the Use of Double-LSB and Signed-LSB Encodings for RNS", Proceedings of 17th International Conference on Digital Signal Processing (DSP), Corfu, Greece, July 6-8, 2011.
E. Vassalos, D. Bakalis and H. T. Vergos, "Modulo 2n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion", Proceedings of 14th Euromicro Conference on Digital System Design: Architectures, Methods & Tools (DSD), pp. 468-475, Oulu, Finland, August 31 - September 2, 2011.
E. Vassalos, D. Bakalis and H. T. Vergos, "Configurable Booth-encoded Modulo 2n±1 Multipliers", Proceedings of 8th Conference on Ph.D. Research in Microelectronics & Electronics (PRIME), pp. 107-110, Aachen, Germany, June 12-15, 2012.
O. Giannou, H. T. Vergos and D. Bakalis, "Squarers in QCA Nanotechnology", Proceedings of 12th International Conference on Nanotechnology (IEEENANO), Birmingham, United Kingdom, August 20-23, 2012.
E. Vassalos, D. Bakalis and H. T. Vergos, "SUT-RNS Residue-to-Binary Converters Design", Proceedings of 15th Euromicro Conference on Digital System Design: Architectures, Methods & Tools (DSD), pp. 65-72, Cesme, Turkey, September 5-8, 2012.
E. Vassalos and D. Bakalis, "On the Design of Modulo 2n-1 Cubing Units", Proceedings of 23rd Great Lakes Symposium on VLSI (GLSVLSI), pp. 251-256, Paris, France, May 2-3, 2013.
E. Vassalos, D. Bakalis and H. T. Vergos, "Reverse Converters for RNSs with Diminished-one Encoded Channels", Proceedings of IEEE Region 8 Conference EUROCON (EUROCON), pp. 1798-1805, Zagreb, Croatia, July 1-4, 2013.
E. Vassalos and D. Bakalis, "Modulo 2n-2 Arithmetic Units", Proceedings of IEEE Region 8 Conference EUROCON (EUROCON), pp. 1806-1813, Zagreb, Croatia, July 1-4, 2013.
E. Vassalos, D. Bakalis and H. T. Vergos, "RNS Assisted Image Filtering and Edge Detection", Proceedings of 18th International Conference on Digital Signal Processing (DSP), Santorini, Greece, July 1-3, 2013.
E. Vassalos and D. Bakalis, "Residue-to-Binary Converter for the New RNS Moduli Set {22n-2,2n-1,2n+1}", Proceedings of Panhellenic Conference on Electronics & Telecommunications (PACET), Volos, Greece, November 8-9, 2019.
D. Bakalis and H. T. Vergos, "Efficient Modulo 2n-4 Arithmetic Units", Proc. of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 234-238, Kalamata, Greece, July 6-9, 2025.
