Πανεπιστήμιο Πατρών

Πρόγραμμα Κ. Καραθεοδωρή 2010-2013

Σχεδίαση ψηφιακών κυκλωμάτων για το αριθμητικό σύστημα υπολοίπων

Συμμετέχοντες

• Δημήτριος Μπακάλης (Επίκουρος Καθηγητής τμήματος Φυσικής, Επιστημονικός Υπεύθυνος)

• Χαρίδημος Βέργος (Αναπληρωτής Καθηγητής τμήματος Μηχανικών Η/Υ και Πληροφορικής)

• Ευάγγελος Βασσάλος (Υποψήφιος διδάκτορας τμήματος Φυσικής)

Διάρκεια

• 01/2011-12/2013 (36 μήνες)

Περιγραφή

Στόχος του έργου είναι η ανάπτυξη καινοτόμων ψηφιακών κυκλωμάτων για το αριθμητικό σύστημα υπολοίπων (Residue Number System - RNS), που θα επιτυγχάνουν χαρακτηριστικά υψηλής ταχύτητας, μικρής επιφάνειας ολοκλήρωσης και χαμηλής κατανάλωσης ισχύος.

Δημοσιεύσεις

1. D. Bakalis, H. T. Vergos and A. Spyrou, "Efficient Modulo 2n+1 Squarers", Integration, the VLSI Journal, Elsevier, vol. 44, no. 3, pp. 163-174, June 2011.

2. E. Vassalos, D. Bakalis and H. T. Vergos, "On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors", Circuit, Systems and Signal Processing, Springer, vol. 30, no. 6, pp. 1445-1461, December 2011.

3. H. T. Vergos and D. Bakalis, "Area-Time Efficient Multi-Modulus Adders and their Applications", Microprocessors and Microsystems, Elsevier, vol. 36, no. 5, pp. 409-419, July 2012.

4. E. Vassalos and D. Bakalis, "Efficient architectures for modulo 2n-2 arithmetic units", International Journal of Electronics, Taylor & Francis, vol. 102, no. 12, pp. 2062-2074, December 2015.

5. E. Vassalos, D. Bakalis and H. T. Vergos, "On the Use of Double-LSB and Signed-LSB Encodings for RNS", Proc. of 17th International Conference on Digital Signal Processing (DSP), Corfu, Greece, 6-8 July 2011.

6. E. Vassalos, D. Bakalis and H. T. Vergos, "Modulo 2n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion", Proceedings of 14th Euromicro Conference on Digital System Design: Architectures, Methods & Tools (DSD), pp. 468-475, Oulu, Finland, August 31 - September 2, 2011.

7. E. Vassalos, D. Bakalis and H. T. Vergos, "Configurable Booth-encoded Modulo 2n±1 Multipliers", Proceedings of 8th Conference on Ph.D. Research in Microelectronics & Electronics (PRIME), pp. 107-110, Aachen, Germany, June 12-15, 2012.

8. E. Vassalos, D. Bakalis and H. T. Vergos, "SUT-RNS Residue-to-Binary Converters Design", Proceedings of 15th Euromicro Conference on Digital System Design: Architectures, Methods & Tools (DSD), pp. 65-72, Cesme, Turkey, September 5-8, 2012.

9. E. Vassalos and D. Bakalis, "On the Design of Modulo 2n-1 Cubing Units", Proceedings of 23rd Great Lakes Symposium on VLSI (GLSVLSI), pp. 251-256, Paris, France, May 2-3, 2013.

10. E. Vassalos, D. Bakalis and H. T. Vergos, "Reverse Converters for RNSs with Diminished-one Encoded Channels", Proceedings of IEEE Region 8 Conference EUROCON (EUROCON), pp. 1798-1805, Zagreb, Croatia, July 1-4, 2013.

11. E. Vassalos and D. Bakalis, "Modulo 2n-2 Arithmetic Units", Proceedings of IEEE Region 8 Conference EUROCON (EUROCON), pp. 1806-1813, Zagreb, Croatia, July 1-4, 2013.

12. E. Vassalos, D. Bakalis and H. T. Vergos, "RNS Assisted Image Filtering and Edge Detection", Proceedings of 18th International Conference on Digital Signal Processing (DSP), Santorini, Greece, July 1-3, 2013.