Papers
A Vertical-Cell-Transistor (VCT)-Based 4F2 DRAM with Cell-on-Peripheral (COP) Architecture Using Wafer-to-Wafer Hybrid Copper Bonding, IEEE Int. Solid-State Circuits Conf. (ISSCC), 2026.
A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme, IEEE Int. Solid-State Circuits Conf. (ISSCC), 2026.
A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM, IEEE Solid-State Circuits Letters, 2025.
An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier, IEEE J. Solid-State Circuits (JSSC), 2025.
A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration, IEEE J. Solid-State Circuits (JSSC), 2024.
A 4 ns settling time FVF-based fast LDO using bandwidth extension techniques for HBM3, IEEE J. Solid-State Circuits (JSSC), 2024.
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM, IEEE Symp. VLSI Technology and Circuits (SOVC), 2024.
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications, IEEE Asian Solid-State Circuits Conf. (ASSCC), 2023.
A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a highly-accurate duty corrector and NBTI-tolerant DLL, IEEE Int. Solid-State Circuits Conf. (ISSCC), 2023.
A 16-Gb/s/wire 4-wire short-haul transceiver with balanced single-ended signaling (BASES) in 28-nm CMOS, IEEE Trans. Circuits and Systems-II, 2023.
An 8b9b 77.44-Gb/s noise-immune spatial-delta coded transceiver for short-reach memory interfaces in 28-nm CMOS, IEEE Trans. Circuits and Systems-II, 2023.
A 12-Gb/s baud-rate clock and data recovery with 75% phase-detection probability by precoding and integration-hold-reset frontend, IEEE Trans. Circuits and Systems-II, 2023.
A low EMI characteristic of LPDDR5 SDRAM with edge-placed PADs and short re-distribution lines, IEEE Int. Symp. Electromagnetic Compatibility & Signal/Power Integrity, 2022.
Digital low-dropout regulator with voltage-controlled oscillator-based control, IEEE Trans. Power Electronics, 2022.
A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process, IEEE Int. Solid-State Circuits Conf. (ISSCC), 2022.
A 3.2-12.8 Gb/s duty-cycle compensating quadrature error corrector for DRAM interfaces, with fast locking and low power characteristics, IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), 2021.
A reflection and crosstalk canceling continuous-time linear equalizer for high-speed DDR SDRAM, IEEE Symp. VLSI Circuits (SOVC), 2021.
Solar energy-harvesting buck–boost converter with battery-charging and battery-assisted modes, IEEE Trans. Industrial Electronics, 2021.
A 6-Gb/s wireline receiver with intrapair skew compensation and three-tap decision-feedback equalizer in 28-nm CMOS, IEEE Trans. VLSI Systems, 2020.
Time-domain operational amplifier with voltage-controlled oscillator and its application to active-RC filter, IEEE Trans. Circuits and Systems-II, 2020.
Voltage-mode PAM4 driver with differential ternary R-2R DAC architecture, IET Electronics Letters, 2020.
Time-domain analog signal processing techniques, J. Semiconductor Engineering, 2020.
Time-based digital LDO regualtor with fractionally controlled power transistor strength and fast transient response, IEEE Asian Solid-State Circuits Conf. (ASSCC), 2019.
A 12-Gb/s Continuous-time Linear Equalizer with Offset Canceller, J. Semiconductor Technology and Science, 2019.
A current-mode hysteretic buck converter with multiple-reset RC-based inductor current sensor, IEEE Trans. Industrial Electronics, 2019.
A 4-MHz bandwidth continuous-time sigma-delta modulator with stochastic quantizer and digital accumulator, IEEE Trans. Circuits and Systems-II, 2019.
A time-domain controlled current-mode buck converter with wide output voltage range, IEEE J. Solid-State Circuits (JSSC), 2019.
Time-based digital LDO regulator with fractionally controlled power transistor strength and fast transient response, IEEE Asian Solid-State Circuits Conf. (ASSCC), 2019.
A Programmable Logic-in-memory (LiM) based on Magnetic Tunneling Junction (MTJ), J. Semiconductor Technology and Science, 2018.
A 10-MHz time-domain controlled current-mode buck converter with 8.5-% to 93-% switching duty cycle, IEEE Int. Solid-State Circuits Conf. (ISSCC), 2018.
A non-volatile ternary content-addressable memory cell for low-power and variation-tolerant operation, IEEE Trans. Magnetics, 2018.
A fREF/5 bandwidth type-II charge-pump phase-locked loop with dual-edge phase comparison and sampling loop filter, IEEE Microwave and Wireless Components Letters, 2018.
Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation, Int. J. Circuit Theory and Applications, 2018.
Balanced single-ended signaling (BASES) scheme for wire-efficient high-bandwidth wireline interface, IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS), 2018. (Best Poster Paper Award).
A Continuous-time Sigma-delta Modulator with Clock Jitter Tolerant Self-resetting Return-to-zero Feedback DAC, J. Semiconductor Technology and Science, 2018.
A HDMI-to-MHL Video Format Conversion System-on-Chip (SoC) for Mobile Applications, J. Semiconductor Technology and Science, 2018.
A 12-Gb/s HDMI 2.1 quarter-rate transmitter in 28-nm bulk CMOS process, Analog Integrated Circuits and Signal Processing, 2018.
A stochastic flash analog-to-digital converter linearized by reference swapping, IEEE Access, 2017.
Variation-tolerant non-volatile ternary content addressable memory with magnetic tunnel junction, J. Semiconductor Technology and Science, 2017.
A simultaneously bidirectional inductively coupled link in a 130-nm CMOS technology, Int. J. Circuit Theory and Applications, 2017.
Duty-cycle and phase spacing error correction circuit for high-speed serial link, IEICE Electronics Express, 2017.
Quasi-resonant (QR) controller with adaptive switching frequency reduction scheme for flyback converter, IEEE Trans. Industrial Electronics, 2016.
A single-ended simultaneous bidirectional transceiver in 65-nm CMOS technology, J. Semiconductor Technology and Science, 2016.
Wireless power charger for wearable medical devices with in-band communication, Int. J. Circuit Theory and Applications, 2016
Skew cancellation technique for > 256-GByte/s high-bandwidth memory (HBM), IET Electronics Letters, 2016.
A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology, IEEE Int. Conf. Consumer Electronics, 2016.
Switching battery charger integrated circuit for mobile devices in a 130-nm BCDMOS process, IEEE Trans. Power Electronics, 2016.
A multiphase synchronous buck converter with a fully integrated current balancing scheme, IEEE Trans. Power Electronics, 2015.
A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology, Analog Integrated Circuits and Signal Processing, 2015.
A switch-mode boost DC–DC converter for IR drop compensation of charging cable, Int. J. Circuit Theory and Applications, 2015.
Crosstalk cancelling voltage mode driver for multi Gbps parallel DRAM interface, Int. J. Circuit Theory and Applications, 2015.
Variation-tolerant sensing circuit for spin-transfer torque MRAM, IEEE Trans. Circuits and Systems-II, 2015.
A 40-W Flyback Converter with Dual-Operation Modes for Improved Light Load Efficiency, J. Semiconductor Technology and Science, 2015.
A 5.25V-tolerant bidirectional I/O circuit in a 28nm CMOS process, Int. J. Circuit Theory and Applications, 2015.
A 6-Gbps/lane receiver for a clock‐forwarded link in 65nm CMOS process, Int. J. Circuit Theory and Applications, 2015.
An analog sigma-delta modulator with shared operational amplifier for low-power class-D audio amplifier, IEICE Electronics Express, 2015.
Patents
Receiving Circuit, US Patent Application 18/975,461
Memory Device Including Merged Sub-Array, US Patent Application 19/008,328
Memory Core Circuit Having Cell on Periphery (COP) Structure and Memory Device Including the Same, US Patent Application 18/767,238
Semiconductor Device, US Patent 12,300,352
Memory Device, US Patent Application 18/734,650
Memory Device and Memory Module Including the Same, US Patent Application 18/818,007
Memory Device and Memory System, US Patent Application 18/806,022
Clock Multiplexing Circuit, US Patent Application 18/922,797
Semiconductor Device with Adjustment of Phase of Data Signal and Clock Signals, and Memory System Including the Same, US Patent 12,205,668
Semiconductor Memory Device and Memory System Including the Same, US Patent 12,009,057
Memory Device Adjusting Skew of Multi-Phase Clock Signals, Memory Controller Controlling the Memory Device, and Operating Method of the Memory Device, US Patent Application 18/326,657
Memory Devices, Memory Systems Having the Same, and Operating Methods Thereof, US Patent 11,948,621
Interface Circuit and Operating Method Thereof to Compensate for Supply Voltage Variations, US Patent 11,804,841
Planar T-Coil and Integrated Circuit Including the Same,” US Patent Application 17/856,394
Transmitter Transmitting Signals to Channels, Receiver Receiving Signals from Channels, and Semiconductor System Including the Transmitter and the Receiver, US Patent 11,996,935
Low Power PAM-4 Output Transmitter, US Patent Application 18/345,291
Data Processing Device and Memory System Including the Same, US Patent 11,627,021
Transmitter Transmitting Signals to Channels, Receiver Receiving Signals from Channels, and Semiconductor System Including the Transmitter and the Receiver, US Patent 11,552,730
High-Speed Data Transmitting/Receiving System and Method of Removing Simultaneous Switching Noise and Inter-Symbol Interference, US Patent 11,502,714
Data Transmitting and Receiving System Including Clock and Data Recovery Device and Operating Method of the Data Transmitting and Receiving System, US Patent 11,481,217
Method of Adjusting an UI and User Terminal Using the Same, US Patent 11,262,908
Regulator and Operating Method Thereof, US Patent 11,249,500
Memory Device and Memory System Including the Same, US Patent 11,218,343
Transmitter for Cancelling Simultaneous Switching Noise and Data Transmission Method in the Same, US Patent 10,992,412
Signal Transmission Device and Method, and Signal Reception Device, US Patent 10,924,204
System for Linking and Controlling Terminals and User Terminal Used in the Same, US Patent 10,656,895
Digital Phase Locked Loop, US Patent 10,382,046
Method of Adjusting an UI and User Terminal Using the Same, US Patent 10,331,332
Phase-Locked Loop with High-Bandwidth Using Rising Edge and Falling Edge of Signal, US Patent 10,320,400
Apparatus and Method for Charging Control in Wireless Charging System, US Patent 10,205,353
Semiconductor Device Performing De-Skew Operation, US Patent 10,015,025
Switching Regulator and Controller Thereof, US Patent Application 15/492,082
Apparatus and Method for Charging Control in Wireless Charging System, US Patent 9,793,740
Analog to Digital Converter Including Differential VCO, US Patent 9,768,799
Active Rectifier and Circuit for Compensating for Reverse Current Leakage Using Time Delay Scheme for Zero Reverse Leakage Current, US Patent 9,712,077
Transmitter, US Patent 9,685,952
Apparatus and Method for Wireless Power Reception, US Patent 9,437,362
Active Rectifier with Delay Locked Loop to Compensate for Reverse Leakage and Wireless Power Receiving Apparatus Including Active Rectifier with Delay Locked Loop to Compensate for Reverse Current Leakage, US Patent 9,431,889
System and Method for Linking and Controlling Terminals, US Patent Application 15/052,803
Phase Detector, Phase-Frequency Detector, and Digital Phase Locked Loop, US Patent 9,337,849
Phase Shift Circuit and Power Factor Correction Circuit Including the Same, US Patent 9,270,165
Phase Shift Circuit and Power Factor Correction Circuit Including the Same, US Patent 9,252,655
Power Factor Correction Circuit, US Patent 9,225,235
PFC Control Circuit, Active PFC Circuit and PFC Control Method, US Patent Application 14/515,122
Data Transmitting and Receiving Apparatus and Method, and Solid-State Drive Including the Same, US Patent 8,983,379
Signal Transmission Circuit, US Patent 8,941,411