Publications

Selected Publications in International Journals:

2023


2022

7. Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu "Aging Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2022.3231173.

8. Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv Joshi, Sudeb Dasgupta, Anand Bulusu et al., "Phase Noise Analysis of Separately Driven Ring Oscillators," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, doi: 10.1109/TCSI.2022.3196820

9. Khoirom Johnson Singh, Anand Bulusu, Sudeb Dasgupta.Understanding negative capacitance physical mechanism in organic ferroelectric capacitor Solid-State Electronics Vol 194 Pages 108350 August 2022

10. Sarita Yadav, Nitanshu Chauhan, Raghav Chawla, Arvind Sharma, Shashank Banchhor, Rajendra Pratap, Bulusu Anand.Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs Vol 37 Pages 085023 July 2022.

11. K. J. Singh, N. Chauhan, A. Bulusu and S. Dasgupta, "Physical Cause and Impact of Negative Capacitance Effect in Ferroelectric P(VDF-TrFE) Gate Stack and Its Application to Landau Transistor," in IEEE Open Journal of Ultrasonics, Ferroelectrics, and Frequency Control, vol. 2, pp. 55-64, 2022, doi: 10.1109/OJUFFC.2022.3172665.

12. Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V Joshi, Sudeb Dasgupta, Anand Bulusu et al., "An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 4, pp. 2311-2315, April 2022, doi: 10.1109/TCSII.2022.3149818.

13. K. J. Singh, A. Bulusu and S. Dasgupta, "Origin of Negative Capacitance Transient in Ultrascaled Multidomain Metal-Ferroelectric-Metal Stack and Hysteresis-Free Landau Transistor," in IEEE Transactions on Electron Devices, vol. 69, no. 3, pp. 1284-1292, March 2022, doi: 10.1109/TED.2021.3139057.

14. N. Chauhan, N. Bagga, S. Banchhor, A. Datta, S. Dasgupta and A. Bulusu, "Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits," in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 69, no. 1, pp. 430-437, Jan. 2022, doi: 10.1109/TUFFC.2021.3116897.

15. N. Mishra, L. M. Dani, S. Chakraborty, R. V. Joshi and A. Bulusu, "Delay Modulation in Separately Driven Delay Cells Utilized for the Generation  of High-Performance Multiphase Signals Using ROs," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 1, pp. 30-34, Jan. 2022, doi: 10.1109/TCSII.2021.3081829.

2021

16. Nitanshu Chauhan, Navjeet Bagga, Shashank Banchhor, Chirag Garg, Arvind Sharma, Arnab Datta, S Dasgupta, Anand Bulusu.BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective Nanotechnology Vol 33 Page 085203 December 2021.

17. Sarita Yadav, Nitanshu Chauhan, Shobhit Tyagi, Arvind Sharma, Shashank Banchhor, Rajiv Joshi, Rajendra Pratap, Anand Bulusu.A physical insight into variation aware minimum V DD for deep subthreshold operation of FinFET.Semiconductor Science and Technology Vol 36 Pages 125002October 2021.

18. C. Garg, N. Chauhan, A. Sharma, S. Banchhor, A. Doneria, S. Dasgupta, A. Bulusu, "Investigation of Trap-Induced Performance Degradation and Restriction on Higher Ferroelectric Thickness in Negative Capacitance FDSOI FET," in IEEE Transactions on Electron Devices, vol. 68, no. 10, pp. 5298-5304, Oct. 2021, doi: 10.1109/TED.2021.3105952.

19. L. M. Dani, N. Mishra and B. Anand, "A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 3, pp. 1557-1561, March 2021, doi: 10.1109/TCSII.2021.3106796.

20. C. Garg, N. Chauhan, S. Deng, A. I. Khan, S. Dasgupta, Anand Bulusu, Kai Ni, "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET," in IEEE Electron Device Letters, vol. 42, no. 8, pp. 1160-1163, Aug. 2021, doi: 10.1109/LED.2021.3087335.

21. Shashank Banchhor, Nitanshu Chauhan, Bulusu Anand.A new physical insight into the zero-temperature coefficient with self-heating in silicon-on- insulator fin field-effect transistors Semiconductor Science and Technology Vol 36 Page 035005 . January 2021

22. L. M. Dani, N. Mishra and A. Bulusu, "An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor- Based VCO Architectures," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 10, pp. 2117-2127, Oct. 2021, doi:10.1109/TCAD.2020.3037881.

2020

23. K. J. Singh, A. Bulusu and S. Dasgupta, "Multidomain Negative Capacitance Effect in P(VDF-TrFE) Ferroelectric Capacitor and Passive Voltage Amplification," in IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4696-4700, Nov. 2020, doi: 10.1109/TED.2020.3022745. 

24. N. Mishra, L. M. Dani, K. Sanvaniya, S. Dasgupta, S. Chakraborty and A. Bulusu, "Design and Realization of High-Speed Low-Noise Multi-Loop  Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 11, pp. 2352-2356, Nov. 2020, doi: 10.1109/TCSII.2019.2959573.

25. Chaudhry I. Kumar and Bulusu Anand, "A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design, Accepted for pubilcation in IEEE Transactions on Device and Material Reliability. 

2019

26. Lalit Dani, N. Mishra, A. Sharma, Bulusu Anand, “Variation Aware Prediction of Circuit Performance in Near-threshold Regime using Supply Independent Transition Threshold Points,” IEEE Transactions on Electron Devices, December, 2019.

27. C. I. Kumar and B. Anand, "A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design," in IEEE Transactions on Nuclear Science, vol. 66, no. 10, pp. 2196-2206, Oct. 2019, doi: 10.1109/TNS.2019.2939380.

28. A. Acharya, A. B. Solanki, S. Glass, Q. T. Zhao and B. Anand, "Impact of Gate–Source Overlap on the Device/Circuit Analog Performance of Line TFETs," in IEEE Transactions on Electron Devices, vol. 66, no. 9, pp. 4081-4086, Sept. 2019, doi: 10.1109/TED.2019.2927001.

29. S. Banchhor, K. D. Kumar, A. Dwivedi and B. Anand, "A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits," in IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 2863-2868, July 2019, doi: 10.1109/TED.2019.2914867.

30. C. I. Kumar, I. Bhatia, A. K. Sharma, D. Sehgal, H. S. Jatana and A.Bulusu, "A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 9, pp. 2170-2179, Sept. 2019, doi: 10.1109/TVLSI.2019.2910825.

31. Chaudhry Indra Kumar, Anand Bulusu High performance energy efficient radiation hardened latch for low voltage applications ” Elsevier Integration Journal pp. 119-127 May 2019 

32. Chaudhry Indra Kumar, Arvind Kumar Sharma, RajendraPartap, Anand Bulusu, “An energy-efficient variation aware self-correcting latch,” Elsevier Microelectronics Journal, pp. 67 – 78, to be published in February 2019.

2018

33. Chaudhry Indra Kumar and Bulusu Anand, “Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell,” IET Electronics Letters, pp. 1423 – 1424, December 2018.

34. Arvind Sharma, Naushad Alam and Anand Bulusu, “Effective Drive Current for Near-Threshold CMOS Circuits’ Performance Evaluation: Modeling to Circuit Design Techniques,” IEEE Transactions on Electron Devices, pp. 2413 – 2421, June 2018.

35. Abhishek Acharya, Abhishek Solanki, Sudeb Dasgupta and Bulusu Anand, “Drain Current Saturation in Line Tunneling-Based TFETs: An Analog Design Perspective,” IEEE Transactions on Electron Devices, Volume: 65, Issue: 1, Jan. 2018.

2017

36. Om Prakash , Satish Maheshwaram, Mohit Sharma Anand Bulusu , Sanjeev K. Manhas, “Performance and Variability Analysis of SiNW 6T- SRAM Cell using Compact Model with Parasitics,” IEEE Transactions on Nanotechnology , Volume: 16, Issue: 6, Nov. 2017.

37. Arvind Sharma, Naushad Alam and Anand Bulusu, “Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design,” IEEE Transactions on Electron Devices, October 2017.

38. Om Prakash, Swen Beniwal, Satish Maheshwaram, Anand Bulusu, Navab Singh, and S. K. Manhas, “Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits,” IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 17, NO. 2, JUNE 2017

39. Abhishek Acharya, S. Dasgupta, Bulusu Anand, “A Novel VDSAT Extraction Method forTunnel FETs and its Implication on Analog Design” IEEE Transactions on Electron Devices, February 2017.

2016

40. Arvind Sharma, Naushad Alam, Sudeb Dasgupta, Bulusu Anand, “Multifinger MOSFETs’ Optimization Considering Stress and INWE in Static CMOS Circuits”, IEEE Transactions on Electron Devices, PP, no. 99, 2016.

41. Baljit Kaur, Arvind Sharma, Naushad Alam, Sanjeev K. Manhas, Bulusu Anand, “A Variation Aware Timing Model for a 2-Input NAND Gate and Its Use in Sub-65nm CMOS Standard Cell Characterization”, Microelectronics Journal (Elsevier), vol. 53, pp. 45-55, 2016.

42. Archana Pandey; Harsh Kumar; S. K. Manhas; Sudeb Dasgupta; Bulusu Anand, “Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and significance”, IEEE Transactions on Electron Devices, pp. 1392-1396, march 2016.

2014

43. Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand, “Efficient ECSM characterization considering voltage, temperature and mechanical stress variability,” IEEE Transactions on Circuits and Systems – I, pp. 3407-3415, December 2014.

44. Gaurav Kaushal, S. K. Manhas, S. Maheshwaram, S. Dasgupta, B. Anand, and N. Singh, “Novel Design Methodology Using Lext Sizing in Nanowire CMOS Logic” IEEE Transactions on Nanotechnology, pp. 650-658, July 2014.

45. Naushad Alam, Bulusu Anand and Sudeb Dasgupta, “ An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design,” IEEE Transactions on Circuits and Systems – I, pp. 1714-1726, June 2014.

46. Archana Pandey, Bulusu Anand, Swati Raycha, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, “Effect of Load Capacitance and Input Transition Time on Underlap FinFET Capacitance,” IEEE Transactions on Electron Devices, pp. 30-36, January 2014.

47. Ashwani Kumar, Vishvendra Kumar, Bulusu Anand, S. Manhas, “Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance,” IEEE Transactions on Nanotechnology, pp. 16- 22, January 2014.

2013

48. S. Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, “Vertical Nanowire CMOS Parasitic Modeling and its Performance  Analysis,” IEEE Transactions on Electron Devices, vol. 60, no. 9, pp. 2943-2950, Sept. 2013.

49. Menka, Bulusu Anand and Dasgupta S., “Two Dimensional Analytical Modeling for Asymmetric 3T and 4T Double Gate Tunnel FET in Subthreshold Region: Potential and Electric Field”, Microelectronics Journal (In press).

50. N. Alam, B. Anand, and S. Dasgupta, “The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Variable Taper CMOS Buffer Design", Elsevier Microelectronics Reliability, vol. 53, Issue 5, pp. 718-724, May 2013.

51. N. Alam, B. Anand, and S. Dasgupta, “The Impact of Process-Induced Mechanical Stress on CMOS Buffer Design using Multi-Fingered Devices", Elsevier Microelectronics Reliability, vol. 53, Issue 3, pp. 379- 385, March 2013.

2012

52. N. Alam, B. Anand, and S. Dasgupta, "Gate-Pitch Optimization for Circuit Design using Strain-Engineered Multi-Finger Gate Structures", IEEE Transactions on Electron Devices, vol. 59, no. 11, pp. 3120-3123, November 2012.

53. Gaurav Kaushal, S. Manhas, S. Maheshwaram, S. Dasgupta, A. Bulusu and N. Singh, “Tuning source/drain extension profile in current matching in nanowire CMOS logic,” IEEE Transactions in Nanotechnology, vol. 11, no. 5, pp. 1033-1035, September 2012.

54. Satish Maheshwaram, S. K. Manhas, G. Kaushal, B. Anand and N. Singh, "Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform," IEEE Electron Device Letters, vol.33, no. 7, pp.934-936, July 2012.


2011

55. Satish Maheshwaram, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, and NavabSingh, “Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS,” IEEE Electron Device Letters, pp. 1011-1013, August 2011.


2009

56. Pradeep Kumar Chawda, B. Anand, V. Ramgopal Rao, “Optimum Body Bias constraints for leakage reduction in high-K Complementary Metal Oxide Semiconductor Circuits,” Japanese Journal of Applied Physics (JJAP), May 2009.


2004

57. Bulusu Anand, M. P. Desai, and V. Ramgopal Rao, "Silicon Film Thickness Optimization for SOI-DTMOS from Circuit Performance considerations", IEEE Electron Device Letters, pp. 436-438, June 2004.


2002

58. P. Sivaram, B. Anand, M. P. Desai, “Silicon film thickness considerations for SOI-DTMOS,” IEEE Electron Device Letters, pp. 276-278, May 2002.



Selected Publications in International Conferences:

2024

1.   A. Kumar, M. Ehteshamuddin, A. Bulusu, S. Mehrotra, and A. Dasgupta, “A Physics-based Compact Model for ULTRARAM Memory Device,” IEEE Electron         Devices Technology and Manufacturing Conference (EDTM), 2024. 

2.  A. Kumar, A. Bulusu, and A. Dasgupta, “Performance Projection of Negative Capacitance Complementary FET (NC-CFET): Device-Circuit Co-design,” IEEE          Electron Devices Technology and Manufacturing Conference (EDTM), 2024.

2023

3.   A. Kumar, A. Bulusu, S. Mehrotra, and A. Dasgupta, “A Landau Based Compact Model for Multi Domain Ferroelectric Field Effect Transistors,” International       Workshop on Physics of Semiconductor Devices (IWPSD), 2023.

4.  Nitanshu Chauhan, Amit Kumar Behera, Chirag Garg, Sudeb Dasgupta, Anand Bulusu "Impact of Non-Uniform Ferroelectric Dielectric Phase and Metal                 Grains on the Performance of MFM Capacitor and Ferroelectric FETs," 2023 IEEE International Symposium on Applications of Ferroelectrics (ISAF),                      Cleveland, OH, USA, 2023, pp. 1-4, doi: 10.1109/ISAF53668.2023.10265412.

5.  Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind                Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu"Beyond SPICE Simulation: A Novel Variability-Aware STA                   Methodology for Digital Timing Closure," 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to         Circuit Design (SMACD), Funchal, Portugal, 2023, pp. 1-4, doi: 10.1109/SMACD58065.2023.10192158.

6.  Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V Joshi, S Dasgupta, Anand Bulusu"A Fully Differential 4-Bit Analog Compute-In-Memory Architecture       for Inference Application," 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hangzhou, China, 2023, pp. 1-5,          doi: 10.1109/AICAS57966.2023.10168599.

8.  Dinesh Kushwaha, Ashish joshi, Neha gupta, aditya sharma, Sandeep miryala, Rajiv Joshi, Sudeb Dasgupta and Anand bulusu “An Energy - Efficient Multi-bit       current-based Analog Compute in Memory Architecture and Design Methodology,” VLSI Design Conference, January 2023, Hyderabad.

9. Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta, “Radiation Hardened CMOS Programmable Bias Generator for Space Applications at                 180nm,” VLSI Design Conference, January 2023, Hyderabad.

2022

10. A. Kumar, G. Pahwa, A. K. Behera, A. Bulusu, S. Mehrotra, and A. Dasgupta, “Analysis and Modeling of Flicker Noise in Ferroelectric FinFETs,” 2022 IEEE           International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1-5.

11  .Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta et al., "Design optimization Using             Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin- FET for Mid- Band 5G Applications," 2022 35th International Conference on VLSI              Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022, pp. 292-296, doi: 10.1109/VLSID2022.2022.00063.

12.  Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu "A Multibit MAC Scheme using                     Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture," 2022 29th IEEE International Conference on Electronics,                  Circuits  and Systems (ICECS), 2022, pp. 1-4, doi: 0.1109/ICECS202256217.2022.9970819.

13. S. Manikandan, N. Chauhan, N. Bagga, A. Kumar, S. Banchhor, S. Roy, A. Bulusu, A. Dasgupta, and S. Dasgupta “Analysis and Modeling of Leakage Currents        in Stacked Gate-All-Around Nanosheet Transistors,” 2022 IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1-4.

14. N. Chauhan et al., "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative                         Capacitance FDSOI," 2022 IEEE International Reliability Physics Symposium (IRPS), 2022, pp. P23-1-P23-6, doi: 10.1109/IRPS48227.2022.9764552. 

2021

15. B. S. Prakash, A. Yadav, A. Bulusu and S. Dasgupta, "A Novel High RSNM RHBD 16T SRAM Cell at 180nm," 2021 IEEE 18th India Council International Conference (INDICON), 2021, pp. 1-5, doi: 10.1109/INDICON52576.2021.9691597.

16. A. Yadav, A. Bulusu, S. Dasgupta and S. Singh, "Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm," 2021 International Conference on Microelectronics (ICM), 2021, pp. 166-169, doi: 10.1109/ICM52667.2021.9664963.

17. S. Yadav, N. Chauhan, A. Pandey, R. Pratap and A. Bulusu, "Behaviour of FinFET Inverter’s Effective Capacitances in Low-Voltage Domain," 2021 25th International Symposium on VLSI Design and Test (VDAT), 2021, pp. 1-5, doi:10.1109/VDAT53777.2021.9601052.

18. K. J. Singh, A. Bulusu and S. Dasgupta, "Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5, doi: 10.1109/ISCAS51556.2021.9401100.

19. K. J. Singh, A. Bulusu and S. Dasgupta, "Ultrascaled Multidomain P(VDF-TrFE) Organic Ferroelectric Gate Stack to the Rescue," 2021 IEEE Latin America Electron Devices Conference (LAEDC), 2021, pp. 1-4, doi: 10.1109/LAEDC51812.2021.9437926.

20. S. Banchhor, N. Chauhan, A. Doneria and B. Anand, "Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect," 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID), 2021, pp. 199-203, doi: 10.1109/VLSID51830.2021.00039.

21. L. C. Acharya, A. k. Sharma, V. Ramakrishan, A. Mandal, S. Dasgupta and A. Bulusu, "Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization," 2021 22nd International Symposium on Quality Electronic Design (ISQED), 2021, pp. 251-256, doi: 10.1109/ISQED51717.2021.9424341.


2019

22. N. Bagga, N. Chauhan, A. Bulusu and S. Dasgupta, "Demonstration of a Novel Ferroelectric-Dielectric Negative Capacitance Tunnel FET," 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), 2019, pp. 102-105, doi: 10.1109/MOS-AK.2019.8902381.

23. Lalit M. Dani, Neeraj Mishra and Anand Bulusu, “MOS Varactor RO architectures in Near Threshold Regime using Forward Body Biasing techniques,” VLSI Design Conference, January 2019, Delhi


2018

24. Lalit M. Dani, N. Mishra, S.K. Banchhor, S. Miryala, A. Doneria, Bulusu Anand, “Design andCharacterization of Bulk Driven MOS Varactor Based VCO at Near Threshold Regime,” IEEE-S3S, San Francisco, October 2018.

25. Raghav Chawla, S. Yadav, A. Sharma, B. Kaur, R. Pratap and Bulusu Anand, “TSV Induced Stress Model and Its Application in Delay Estimation,” IEEE- S3S, San Francisco, October 2018.

26. Arvind Sharma, Naushad Alam, Raghav Chawla,Bulusu Anand, “Modeling the effect of variability on the timing response of CMOS inverter-transmission gate structure,” International Symposium on Devices, Circuits and Systems (ISDCS), Howrah.2018

27. C. Inder Kumar and Bulusu Anand “Design and Analysis of Energy-Efficient Self-Correcting Latches Considering Metastability,” IEEE PRIME, July 2018, Prague.

28. A. Sharma, N. Alam, A. Bulusu, “UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit- Device Interaction Perspective,” IEEE PRIME, July 2018, Prague.

29. Archana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu, “A Modified Method of Logical Effort for FinFET Circuits considering of Fin-Extension Efforts,” IEEE ISQED-2018.


2017

30. Abhishek Acharya, Sudeb Dasgupta and Bulusu Anand, Impact of Device Design Parameters on V DSAT and Analog Performance of TFETs,” Accepted for presentation in IEEE Silicon Nanoelectronics Workshop 2017.


2016

31. Archana Pandey, Harsh Kumar, Praanshu Goyal, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand “FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay” , IEEE VLSI Design, 2016.

32. Sayyaparaju Sagar Varma, A. Sharma, Bulusu Anand, " An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis," IEEE SMACD, 2016, Lisbon.

33. Chaudhry Indra Kumar, A. Sharma, S. Miryala, Bulusu Anand, "A novel energy-efficient self-correcting methodology employing INWE," IEEE SMACD, 2016, Lisbon.


2015

34. Arvind Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, and Bulusu Anand, "Pre-layout Estimation of Performance and Design of Basic Analog Circuits in Stress Enabled Technologies" in IEEE VDAT, 2015.

35. Yogesh Chaurasiya, Surabhi Bhargava, Arvind Sharma, Baljit Kaur, and Bulusu Anand, "Timing Model for Two Stage Buffer and Its Application in ECSM Characterization", in IEEE VDAT, 2015.

36. Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta and Bulusu Anand, “Efficient Static D-Latch Standard Cell Characterization Using a Novel Setup Time Model,” Accepted in IEEE ISQED 2015.


2014

37. Parmanand Singh,V. Asthana, R. Sithanandam, A. Bulusu, S. Dasgupta, “Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor,” IEEE VLSI Design, 2014.

38. Bijay Kumar Dalai, A. Bulusu, N. Kannan and Arvind Kumar Sharma, "An Empirical Delta Delay Model for Highly Scaled CMOS Inverter Considering Well Proximity Effect," VDAT 2014.


2013


39. Saurabh K. Nema, M. SaiKiran, P. Singh, Archana Pandey, S. K. Manhas, A. K. Saxena, Anand Bulusu, “Improved Underlap FinFET with Asymmetric Spacer Permittivities,” Accepted in IWPSD 2013.

40. Arvind Kumar Sharma, Naushad Alam, Sudeb Dasgupta and Bulusu Anand, “The Impact of Process-Induced Mechanical Stress on D-Latch Timing Performance,” Accepted in IEEE IMPACT 2013.

41. S. Maheshwaram, S.K. Manhas, G. Kaushal, and B. Anand, “Vertical Nanowire MOSFET Parasitic Resistance Modeling,” in Proc. IEEE EDSSC 2013, Hong Kong.

42. Prahlad Kumar Sahu, R. Sithanandam , Anand Bulusu and Sudeb Dasgupta “TCAD Evaluation of Fin Architecture on SOI Substrate and its Comparison with Planar FDSOI MOSFET at 28nm Technology Node”,” VDAT, 2013.

43. Baljit Kaur, S. Miryala, S. K. Manhas and Bulusu Anand, “An Efficient Method for ECSM Characterization of CMOS Inverter in Nanometer Range Technologies,” Accepted in IEEE International Symposium on Quality Electronic Design (ISQED) 2013.

44. Archana Pandey, Swati Raycha, Satish Maheshwaram, S. K. Manhas, S. Dasgupta, Bulusu Anand, “Underlap FinFET Capacitance: Impact of Input Transition Time and Output Load” IEEE International Nanoelectronics Conference (INEC) 2013.


2012

45. Menka, Bulusu Anand and Dasgupta S., “A TCAD approach to evaluate channel electrondensity of double gate symmetric n-tunnel FET”, INDICON 2012, pp:577-581. 37. N. Alam, B. Anand, and S. Dasgupta, “Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance”, in IEEE ISQED, 2012, pp. 717-720.

46. N. Alam, B. Anand, and S. Dasgupta, “Impact of Dummy Poly on the Process- Induced Mechanical StressEnhanced Circuit Performance", in VDAT 2012, pp. 357- 359.


2011

47. N. Alam, S. Dasgupta, and B. Anand “Impact of process-induced mechanical stress on multi-fingered device performance”, in Proc. IWPSD, 2011. 

48. Arnab Kumar Biswas, Anand Bulusu and Sudeb Dasgupta, “A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz,” Proceedings of IEEE ISVLSI 2011.

49. Sandeep Miryala, Baljeeth Kaur, Bulusu Anand and Sanjeev Manhas, "Efficient Nanoscale VLSI Standard Cell Library Characterization Using a Novel Delay Model," Proceedings of IEEE ISQED 2011.


2010

50. Saurabh Nema, Mayank Srivastava, Angada B. Sachid, A. K. Saxena, Anand Bulusu, "A Novel Scaling Strategy for Underlap FinFETs," ICCCD 2010, IIT Kharagpur.


2007

51. Bulusu Anand, V. Ramgopal Rao and M. P. Desai, "Circuit Performance Improvement Using PDSOI- DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics,” Accepted in VLSI- DAT, 2007.


52. Bulusu Anand, V. Ramgopal Rao and M. P. Desai, "Circuit Performance Improvement Using PDSOI- DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics,” Accepted in VLSI- DAT, 2007.


2004

53. Pradeep Kumar Chawda, B. Anand, and V.Ramgopal Rao, "Effectiveness of Optimum Body Bias for Leakage Reduction in High K CMOS Circuits",Proceedings of 35th International Conference on Solid State Devices and Materials (SSDM 2004), pp. 434-435, Tokyo, Japan, September 15-17, 2004.

54. Pradeep Kumar Chawda, B. Anand, and V.Ramgopal Rao, "Effectiveness of Optimum Body Bias for Leakage Reduction in High K CMOS Circuits", Proceedings of 35th International Conference on Solid State Devices and Materials (SSDM 2004), pp. 434-435, Tokyo, Japan, September 15-17, 2004.


1999

55. Sushant Suryagandh, B. Anand, M. P. Desai and V. Ramgopal Rao, “Dynamic Threshold Voltage CMOS (DTMOS) for Future Low Power Sub-1V Applications," Proceedings of 10th International Workshop on Physics of Semiconductor Devices (IWPSD), pp. 655-658, December 1999, New Delhi.


56. Sushant Suryagandh, B. Anand, M. P. Desai and V. Ramgopal Rao, “Dynamic Threshold Voltage CMOS (DTMOS) for Future Low Power Sub-1V Applications," Proceedings of 10th International Workshop on Physics of Semiconductor Devices (IWPSD), pp. 655-658, December 1999, New Delhi.

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