Development of A Stability & Reliability Aware Design Methods for Sram Based CIM for AI Applications
PI: Anand Bulusu
Sponsor: SRC Cost: Rs.$70,000 Lakh Status : (Ongoing)
Description:
A Systematic Design of Robust Memory Cell Using Ferroelectric FET (FeFET) for AI Hardware Accelerator.
PI: Anand Bulusu
Sponsor: SERB Cost: Rs. 15 Lakh Status : (Ongoing)
Description: This project is geared towards pioneering a cutting - edge FeFET bit cell/array design methodology tailored for computational -in memory (CIM) application. Our objective is to propose a model for efficiant evaluation of ferroelectric parameters for designing robust FeFET memory array for use as an NVM as well as in CIM.
Open-based reliable and robust framework for accurate timing sign-off with reduced design margins of digital integrated circuits.
PI: Anand Bulusu
Sponsor: (RESEARCH SOLUTIONS OPERATION) Cost: Rs. 24.81 Lakh Status : (Ongoing)
Description: This work aims to develop an OPENSTA based robust framework considering reliability for accurate timing sign-off with a reduced design margin for digital integrated circuits. The device/layout level variability-aware framework would solve circuit-level design issues for operation at multiple supply voltage points while reducing design margins and design iterations.
Nanoscale FinFET device and circuit design methodology
PI: Anand Bulusu
Sponsor: DST Cost: Rs. 20.40 Lakh Status: Completed
Description: Our aim is to build a quantitative link between device and circuit level performance of FinFETs. We propose to do this by developing models of FinFET device parasitics and using these to develop circuit delay and power models.
A robust methodology for nanoscale VLSI circuit design considering layout dependent systematic variations
PI: Anand Bulusu, Co-PI: Sudeb Dasgupta
Sponsor: DST Cost: Rs. 38.37 Lakh Status: (Ongoing)
Description: Our aim in this project is to model timing performance parameters of circuits with layout parameters in CMOS technologies having process-induced mechanical stress. Using such models, we would propose methods to improve the performance of circuits in such CMOS technologies.
Remote Detection of Humans Trapped Under Debris in Disaster Affected AreasUsing RF Sensing of Cardiopulmonary Motion. (SMPD-C2SD)
PI: Sudeb Dasgupta, Co-PI: Anand Bulusu
Sponsor: MIETY (formerly DIETY) Cost: Rs. 5 Cr. Status: Completed
Description: In this project, we propose an RF sensing based system which can identify the number and depths of living persons trapped inside debris due to disasters such as earthquakes etc. The presence of human life can be ascertained by the virtue of its vital signs such as respiration rate and heartbeats. We propose to use a system applying single band RF sensors with on-chip processing. All the parts of the system (except PA and antenna) would be implemented within a CMOS SoC.
ICT Academy
PI: Sanjeev Manhas Co-PI: Anand Bulusu
Sponsor: MIETY (formerly DIETY) Cost: Rs. 7Cr. Status: (Ongoing)
Description: In this project, the faculty and graduates of academic institutions in Uttarakhand, Himachal and Jammu and Kashmir would be imparted course and skill training.
Advanced MOS Physics and its application to device modeling (Consultancy)
PI: Anand Bulusu
Sponsor: SCL, Chandigarh, ISRO Cost: Rs. 1.7 Lakh Status: Completed
Description: Classes and discussion on advanced MOS physics and modeling for SCL’s CMOS technology.
Development and Efficient Characterization of Floating Body (FB) and Dynamic Threshold (DT) CMOS Partially Depleted Silicon-On-Insulator (PDSOI) Standard Cell Libraries
PI: Anand Bulusu
Sponsor: DST Cost: Rs. 49 Lakhs (Ongoing)
Description: PDSOI technology is being developed in India by SCL Chandigarh for its radiation hard nature. The project aims for the design enablement of the PDSOI technology and its early circuit design for process and PDK improvement. We will consider the PDSOI floating body effects rigorously.
An energy efficient IoT processor build using an optimized near-threshold voltage standard cell library
PI: Anand Bulusu
Sponsor: IMPRINT-2 (DST) Cost: Rs. 54 Lakhs Status: Completed
Description: This project involves the development of a near threshold standard cel library an IoT processor in a 28 nm CMOS process and in SCL’s 180 nm CMOS process.
A robust and scalable VLSI characterization methodology for high performance CMOS designs considering spatial and temporal variations
PI: Anand Bulusu
Sponsor: Semiconductor Research Corporation (SRC) Cost: $48000 (Ongoing)
Description: Timing models of planar CMOS standard cells would be developed. These would estimate spatial and temporal variations through Vth, μ0 and RCs. These are then used to develop an aging-aware and PVT variability aware STA flow.
A Design Methodology of Compute-In-Memory SRAM Macro for AI/ML Applications
PI: S. Dasgupta Co-PI: Anand Bulusu
Sponsor: Semiconductor Research Corporation (SRC) Cost: $36000 (Ongoing)
Description: Circuit design methodology for analog compute-in-memory circuits considering PVT variations.
Development of RadHard 1.8/5V/10V/20V I/O Pads in SCL’s 0.18µm CMOS Process
PI: S. Dasgupta Co-PI: Anand Bulusu
Sponsor: ISRO Cost: Rs. 38 Lakhs (Ongoing)
Description: The main objective of the project is to design an RadHard Input-Output (I/O) Pads in 5V SCL's CMOS process using 5V standard transistors, design of I/O pads in 10/20V using LD-MOS Transistors and the design of 5V-tolerant I/O pads in 3.3V CMOS Process without the need for process options using only 3.3V standard transistors
Design and Development of ROM based low power Al Inference chip
PI: Anand Bulusu
Sponsor: TIH Cost: 1.13 crore (Ongoing)
Description: The main objective of the project is to design a ROM based ultra low power AI inference chip with one-time programming of (trained) weights.
A PDSOI Analog Cell Library Consisting 2 Stage OPAMPS And Comparators Designed Considering Floating Body And Self Heating Effects
PI: Anand Bulusu
Sponsor: ISRO Cost: Rs. 14 Lakhs
Description: The main objective of the project would be to design, fabrication and testing of a library of OP-Amps and comparators using models developed for considering the floating body (FB) and Self-Heating (SH) effects in PDSOI analog/mixed signal circuits, along with the development of a software tool for design of PDSOI Op-Amp and comparators while considering FB and SH effects.
Smart Contactless Technology Development For Smart Fencing (Multi-Institutional)
PI: Anand Bulusu (IITR)
Sponsor: DST Cost: Rs. 22 Lakhs (IITR) (Ongoing)
Description: In this project, we suggest a new coil design that uses a 180W system to wirelessly charge the drone's lithium polymer battery. The goal of maintaining the 180W WPT system is to fully charge the battery in about 20 minutes. WPT's operating frequency was raised from the previous 85 kHz to 100 kHz in order to improve WPT's efficiency and lessen misalignment problems.